Extension for the advanced microcontroller bus architecture...

Details Extension for the advanced microcontroller bus architecture... Extension for the advanced microcontroller bus architecture...

2005-02-15

2005-02-15

Lee, Thomas (Department: 2115)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus expansion or extension

C713S320000, C713S401000, C713S501000

Reexamination Certificate

active

06857037

ABSTRACT:
System (50), e.g. a System on a chip (SoC), comprising a system bus (56), a high-speed functional block (51) operably linked to the system bus (56), and a high-speed clock line (54) for applying a high-speed clock to the high-speed functional block (51). The system (50) further comprises a peripheral bus (59), a low-speed functional block (52) operably linked to this peripheral bus (59), a circuitry (53) for generating a wait signal (PWAIT), a low-speed clock line (57) for applying a low-speed clock (PCLK) to the low-speed functional block (52), a select line (58) for feeding a select signal (PSEL) from the peripheral bus (59) to the low-speed functional block (52), an enable line (55) for applying a clock enable signal (PCLKEN) to the circuitry (53), and a wait line (61) for feeding the wait signal (PWAIT) to the high-speed functional block (51). The circuitry (53) generates the wait signal (PWAIT) from the select line signal (PSEL) and the clock enable signal (PCLKEN).

REFERENCES:
patent: 5499346 (1996-03-01), Amini et al.
patent: 5748806 (1998-05-01), Gates
patent: 6064626 (2000-05-01), Stevens
patent: 6353867 (2002-03-01), Qureshi et al.
patent: 6633994 (2003-10-01), Hofmann et al.

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