Extensible time-sharing bus structure

Details Extensible time-sharing bus structure Extensible time-sharing bus structure

1999-12-30

2002-12-10

Ray, Gopal C. (Department: 2181)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

C709S208000

Reexamination Certificate

active

06493778

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of computer bus structure, and especially to a time-sharing bus structure capable of extending address space.
2. Description of Related Art
Generally, the conventional micro-control system is constructed by a microprocessor, a memory, and I/O devices. As shown in
FIG. 5
, the microprocessor
55
performs data access to the memory
54
by employing an address bus
51
, a data bus
52
and a write/ read control line
53
. The address bus
51
is provided for carrying addresses of the memory
54
(or I/O devices). The width of the address bus
51
thus represents the size of the memory space. For example, a 16-bit address bus, which has 16 address lines, represents that a maximum memory capacity is 64 k bytes.
When the aforesaid micro-control system is desired to increase its memory capacity, the width of the address bus
51
is necessary to be increased. For example, if the memory capacity is increased to 4M bytes, the number of address lines must be increased to 22. As a result, not only the cost of PCB (Printed Circuit Board) is increased, but also the cost of bonding and packaging for the memory is increased. Moreover, after the memory capacity has been designed, it can not be further extended. Therefore, the use of such a memory system is not satisfactory. Accordingly, there is a need to have a novel bus structure that can mitigate and/or obviate the aforementioned problems.
SUMMARY OF THE INVENTION
Accordingly, the primary object of the present invention is to provide an extensible time-sharing bus structure for saving the pin number of an integrated circuit chip.
Another object of the present invention is to provide an extensible time-sharing bus structure for conveniently extending the memory capacity.
In order to achieve the aforesaid objects, there is provided an extensible time-sharing bus structure for transferring data between a master device and at least one slave device. The bus structure has a slave bus interface provided by said slave device and a master bus interface provided by the master device. The master bus interface is connected to the slave bus interface through an address/data bus and at least two control lines. The address/data bus transfers data and address in a time-sharing manner between the master device and the slave device. The at least two control lines are driven by the master device to be at a first logic level or at a second logic level, such that the master device and the slave device utilize the address/data bus for transferring an address, reading data, or writing data, based on a combination of the logic levels of the at least two control lines.
The various objects and advantages of the present invention will be more readily understood from the following detailed description when read in conjunction with the appended drawing.


REFERENCES:
patent: 5191656 (1993-03-01), Forde, III et al.
patent: 5321819 (1994-06-01), Szczepanek
patent: 5793990 (1998-08-01), Jirgal et al.
patent: 5991841 (1999-11-01), Gafken et al.
patent: 6119189 (2000-09-01), Gafken et al.
patent: 6393500 (2002-05-01), Thekkath

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