Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-12-10
2001-04-24
Thomas, Tom (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S310000, C257S303000, C438S240000
Reexamination Certificate
active
06222220
ABSTRACT:
BACKGROUND
1. Technical Field
This disclosure relates to semiconductor fabrication and more particularly, to an extended trench for decreasing interactions between a barrier layer and a high dielectric constant material used in stack capacitor fabrication for semiconductor memories.
2. Description of the Related Art
Semiconductor memory cells include capacitors accessed by transistors to store data. Data is stored by as a high or low bit depending on the state of the capacitor. The capacitor's charge or lack of charge indicates a high or low when accessed to read data, and the capacitor is charged or discharged to write data thereto.
Stacked capacitors are among the types of capacitors used in semiconductor memories. Stacked capacitors are typically located on top of the transistor used to access a storage node of the capacitor as opposed to trench capacitors which are buried in the substrate of the device.
In semiconductor memories, such as dynamic random access memories (DRAM), high dielectric constant capacitor formation processes include deposition of highly dielectric materials. In one type of high dielectric constant capacitors, a layer of high dielectric constant materials, such as barium strontium titanium oxide (BSTO), is deposited in an oxidizing atmosphere.
Referring to
FIG. 1
, a structure
2
with stacked capacitors is shown. Stacked capacitor
3
includes two electrodes a top electrode or storage node
4
, usually platinum (Pt) and a bottom electrode
12
separated by a dielectric layer
18
. An access transistor
5
includes a gate
6
which when activated electrically couples a bitline
7
through a bitline contact
8
to a plug
14
. Plug
14
connects to electrode
12
through a diffusion barrier
16
which stores charge in electrode
12
.
Electrode
12
is separated from plug
14
by diffusion barrier
16
. Plug
14
is preferably polycrystalline silicon (polysilicon or poly). During processing, dielectric layer
18
is deposited on electrode
12
. Dielectric layer
18
is typically a material with a high dielectric constant, for example BSTO. Diffusion barrier
16
is employed to prevent the formation of an oxide layer between electrode
12
and diffusion barrier
16
.
Material properties between dielectric layer
18
and barrier
16
are degraded if materials of the respective layers interact. Further, dielectric layer
18
(BSTO) reacts with diffusion barrier
16
if the compounds in each layer come into contact. Given the proximity of the two materials in the conventional design shown in
FIG. 1
, there is an increased likelihood for this reaction to occur and degrade the properties of stacked capacitor
3
.
Therefore, a need exists for improving capacitance of stacked capacitors by sealing off a barrier to prevent degradation of a high dielectric constant layer and the barrier layer as a result of processing and diffusion. A further need exists for a method of increasing the capacitance of the stacked capacitors by increasing surface area of a bottom electrode.
SUMMARY OF THE INVENTION
A stacked capacitor, in accordance with the present invention includes a conductive plug disposed within a trench for connecting to an access device. A barrier is formed on the plug and is disposed within the trench. A dielectric layer is formed over the trench, the dielectric layer forming a hole therethrough exposing at least a portion of the barrier. A first electrode is formed within the hole and extends from the hole. A capacitor dielectric layer is formed on the first electrode and separating the first electrode from a second electrode, and the dielectric layer and the first electrode substantially prevent chemical interactions of an oxidizing environment employed when forming the capacitor dielectric layer with materials of the barrier.
Another stacked capacitor for semiconductor memories, in accordance with present invention, includes a conductive plug disposed within a trench for connecting to an access transistor. A barrier is formed on the plug and is disposed within the trench. A dielectric layer is formed over the trench, the dielectric layer forming a hole therethrough exposing at least a portion of the barrier. A first electrode is formed within the hole and extends from the hole, the first electrode being formed from a conductive material such that upon depositing the conductive material a contour forms in an upper surface of the conductive layer wherein the contour provides a surface area for a top surface of the first electrode which exceeds a surface area of a substantially flat top surface of the first electrode. A capacitor dielectric layer is contoured on the first electrode and separating the first electrode from a second electrode, and the dielectric layer and the first electrode substantially prevent chemical interactions of an oxidizing environment employed when forming the capacitor dielectric layer with materials of the barrier.
In alternate embodiments, the dielectric layer may include a nitride. The capacitor dielectric layer may includes Barium Strontium Titanium Oxide. The hole in the dielectric layer is intentionally or unintentionally misaligned with the trench such that a portion of the dielectric layer extends over the barrier and a portion of the first electrode extends beyond a trench side wall. The first electrode preferably includes platinum. The dielectric layer is preferably between about 20 nm and about 250 nm in thickness. The barrier preferably includes at least one of TaN, CoSi, TiN, WSi and TaSiN. The contour of the top surface of the first electrode preferably increases a capacitance of the stacked capacitor by between about 2.5% to about 25% over a first electrode having a flat top surface.
A method for fabricating a stacked capacitor includes the steps of providing a plug and a barrier formed on the plug within a trench, the trench being formed in a first dielectric layer, forming a second dielectric layer on the first dielectric layer and on the barrier layer, patterning a hole in the second dielectric layer to expose at least a portion of the barrier, depositing a conductive layer on the second dielectric layer and in the hole, patterning the conductive layer to form a first electrode, forming a capacitor dielectric layer on the first electrode and forming a second electrode on the capacitor dielectric layer.
In other methods, the step of patterning the hole may include the step of patterning the hole to be misaligned with the trench such that a portion of the dielectric layer extends over the barrier and a portion of the first electrode extends beyond a trench side wall. The step of depositing a conductive layer on the second dielectric layer and in the hole may include the step of forming a contour on a top surface of the conductive layer corresponding to a position of the hole. The step of patterning the conductive layer to form a first electrode may include the step of forming the first electrode including the contour on the top surface. The contour of the top surface of the first electrode preferably increases a capacitance of the stacked capacitor by between about 2.5% to about 25% over a first electrode having a flat top surface. The step of forming a second dielectric layer may include the step of forming the dielectric layer with a thickness between about 20 nm and about 250 nm.
These and other objects, features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.
REFERENCES:
patent: 5381302 (1995-01-01), Sandhu et al.
patent: 5392189 (1995-02-01), Fazan et al.
patent: 5654567 (1997-08-01), Numata et al.
patent: 5760434 (1998-06-01), Zahurak et al.
patent: 5915189 (1999-06-01), Sim
patent: 5952687 (1999-09-01), Kawakubo et al.
patent: 0 847 083 (1998-06-01), None
patent: 10-173154 (1998-06-01), None
European Search Report dated May 24, 2000.
Knorr Andreas
Lin Chenting
Owens Douglas W.
Paschburg Donald B.
Siemens Aktiengesellschaft
Thomas Tom
LandOfFree
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