Extended length metal line for improved ESD performance

Details Extended length metal line for improved ESD performance Extended length metal line for improved ESD performance

2005-05-03

2005-05-03

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S355000, C257S173000, C257S174000, C257S297000, C257S328000, C257S357000, C257S358000, C361S301200, 43, C438S618000

Reexamination Certificate

active

06888248

ABSTRACT:
A multi-level metal interconnect structure and method for forming the same for improving a resistance of CMOS transistors to electrostatic discharge (ESD) transient events is disclosed. A semiconductor device including at least one NMOS transistor electrically connected along at least one circuit pathway to an input/output signal source and a reference voltage potential; and, electrically connecting at least the input/output signal source to the at least one NMOS transistor with a metal interconnect line extended in length by compacting at least a portion of the metal interconnect line length portion into a serpentine shape within a predetermined volume of the semiconductor device.

REFERENCES:
patent: 5597758 (1997-01-01), Heim et al.
patent: 5623156 (1997-04-01), Watt
patent: 6147857 (2000-11-01), Worley et al.
patent: 6495442 (2002-12-01), Lin et al.

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