Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2005-10-25
2005-10-25
Beausoliel, Robert (Department: 2113)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
Reexamination Certificate
active
06959404
ABSTRACT:
A data processor timer comprising a writeable control register, a look-up table and a loadable counter. The loadable counter operates in a first mode to load the count data field and operates in a second mode an entry from said look-up table specified by the count data field. The loadable counter generating a time out signal upon counting a number of clock pulses equal to said count. The writeable control register preferably includes a mode bit selecting the first or second modes. This invention is suitable for a pre-scalar counter as part of a data processor watchdog timer.
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patent: 5978939 (1999-11-01), Mizoguchi et al.
patent: 6023776 (2000-02-01), Ozaki
patent: 6173339 (2001-01-01), Yorimitsu
patent: 6260162 (2001-07-01), Typaldos et al.
patent: 6687859 (2004-02-01), Robsman et al.
patent: 6848064 (2005-01-01), Bolz
Hirakawa Katsunobu
Reimer Jay B.
Zhou Weifeng Joe
Beausoliel Robert
Brady III W. James
Duncan Marc M
Marshall, Jr. Robert D.
Telecky , Jr. Frederick J.
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