Extended custom instructions

Electronic digital logic circuitry – Multifunctional or programmable – Having details of setting or programming of interconnections...

Reexamination Certificate

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Details

C708S490000

Reexamination Certificate

active

07112991

ABSTRACT:
Methods and apparatus are provided for efficiently implementing a customizable processor core on a programmable chip. Components of a processor core such as arithmetic logic units, program sequencer units, and address generation units are integrated with customizable logic blocks. Various customizable logic blocks can be invoked in a pipelined manner using an available customized instruction set while allowing a processor to continue simultaneous operation. Program counter snooping is also provided to add custom instruction functionality to a processor with no additional provisions for adding custom instructions.

REFERENCES:
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patent: 6150837 (2000-11-01), Beal et al.
patent: 6477697 (2002-11-01), Killian et al.
patent: 6504398 (2003-01-01), Lien et al.
patent: 6605962 (2003-08-01), Lee et al.
patent: 6633181 (2003-10-01), Rupp
Nios®, “Nios Custom Instructions, Tutorial” by Altera Corporation Doc. Version 1, Jun. 2002, 38 pages.

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