Extendable FIFO

Details Extendable FIFO Extendable FIFO

1991-11-25

1993-11-16

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Serial read/write

36518904, 365233, G11C 700

Patent

active

052629970

ABSTRACT:
An extendable FIFO is disclosed. The FIFO utilizes a quasi-simultaneous clock detector for detecting the activation of READ and WRITE signals and for generating first and second delayed signals in response thereto and a MASK signal when the READ and WRITE signals are substantially simultaneously activated. Additionally, the FIFO includes a plurality of pointer circuits for receiving the first and second delayed signals and the MASK signal and for generating a plurality of clocks and load signals in response thereto. The FIFO further includes a matrix of flip-flops organized into columns which are sequentially connected for receiving the clocks and load signals which control which data column is written into and the sequential transfer of data between columns.

REFERENCES:
patent: 4592019 (1986-05-01), Huang et al.
patent: 4839866 (1989-06-01), Ward et al.
patent: 4888739 (1989-12-01), Frederick et al.
patent: 5005158 (1991-04-01), McClure et al.
patent: 5157633 (1992-10-01), Aoki

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