Exposure pattern forming method and exposure pattern

Details Exposure pattern forming method and exposure pattern Exposure pattern forming method and exposure pattern

2007-04-03

2007-04-03

Do, Thuan (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

11068922

ABSTRACT:
Disclosed is an exposure pattern forming method of forming an exposure pattern by correcting each pattern portion constituting a design pattern by a correction amount, which amount is previously prepared so as to correspond to both a line width of the pattern portion and a space width of a space portion adjacent to the pattern portion, characterized by including the steps of: subjecting the design pattern to graphic form arithmetic operation, to extract each pattern portion for each target line width, and to extract space portion for each target space width; and subjecting each pattern portion extracted for each target line width and the space portion extracted for each target space width to graphic form arithmetic operation based on the corresponding one of the correction amounts, to thereby correct the pattern portion having each target line width for each target space width.

REFERENCES:
patent: 5208124 (1993-05-01), Sporon-Fiedler et al.
patent: 5553273 (1996-09-01), Liebmann
patent: 6077310 (2000-06-01), Yamamoto et al.
patent: 6243855 (2001-06-01), Kobayashi et al.
patent: 5-80486 (1993-04-01), None
patent: 8-28358 (1996-11-01), None
patent: 10-189409 (1998-07-01), None
patent: 11-168065 (1999-06-01), None

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