Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-02-14
2006-02-14
Do, Thuan (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
07000216
ABSTRACT:
The present invention provides an exposure pattern forming method using a rule-based proximity effect correction method to which graphic form arithmetic operation is applied.Disclosed is an exposure pattern forming method of forming an exposure pattern by correcting each of pattern portions constituting a design pattern by a correction amount, which amount is previously prepared so as to correspond to both a line width of the pattern portion and a space width of a space portion adjacent to the pattern portion, characterized by including the steps of: subjecting the design pattern to graphic form arithmetic operation, to extract each of the pattern portions for each of target line widths, and to extract each of the space portions for each of target space widths (ST2, ST3); and subjecting each of the pattern portion extracted for each of the target line widths and the space portion extracted for each of the target space widths to graphic form arithmetic operation based on the corresponding one of the correction amounts, to thereby correct the pattern portion having each of the target line widths for each of the target space widths (ST4to ST9).
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Ogawa Kazuhisa
Ohnuma Hidetoshi
Do Thuan
Kananen Ronald P.
Rader & Fishman & Grauer, PLLC
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