Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Patent
1996-12-09
2000-02-08
Niebling, John F.
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
438160, 438487, H01L 2100
Patent
active
060227648
ABSTRACT:
The present invention discloses a technology for forming a thin film transistor. There is provided an insulating substrate having a gate electrode and a gate insulating layer for protecting the gate electrode thereon. A first semiconductor layer is then formed on the substrate. An insulating layer for etch stopper is formed on the first semiconductor layer and the gate insulating layer. A photoresist film is coated on the whole surface of the resultant structure. A selected portion of the photoreist film is exposed to light by projecting a linear light to a section starting from the backside of the substrate to the photoresist film, the substrate being moved horizontally. Etch stopper layer is formed by developing the exposed photoresist film and then removing the remaining photoresist film.
REFERENCES:
patent: 4830468 (1989-05-01), Stephany et al.
patent: 4857428 (1989-08-01), Koike
patent: 5159476 (1992-10-01), Hayashi
patent: 5311041 (1994-05-01), Tominaga et al.
patent: 5336930 (1994-08-01), Quach
patent: 5391507 (1995-02-01), Kwasnick et al.
patent: 5440189 (1995-08-01), Nakahata et al.
patent: 5712191 (1998-01-01), Nakajima et al.
patent: 5716759 (1998-02-01), Badehi
Wolf, S., Tauber R.N.; Silicon Processing for the VLSI Era vol. 1: Process Technology, Lattice Press, Sunset Beach, CA, p.p. 520-521, Jan. 1986.
Patent Abstracts of Japan, Publication No. 8-172043, Jul. 2, 1996.
Patent Abstracts of Japan, Publication No. 8-29809. Feb. 2, 1996.
Patent Abstract of Japanese Laid-Open No. 62-20375, Jan. 28, 1987.
Patent Abstract of Japanese Laid-Open No. 62-190768, Aug. 20, 1987.
Patent Abstact of Japanese Laid-Open No. 3-154352, Jul. 2, 1991.
Patent Abstract of Japanese Laid-Open No. 3-283529, Dec. 13, 1991.
Patent Abstracts of Japan, Publication No. 6-273799, Sep. 30, 1994.
Patent Abstracts of Japan, Publication No. 8-220769, Aug. 30, 1996.
Derwent Abstract of KR 94-10929.
Jang Jong-Seok
Park Cheol-Hee
Hyundai Electronics Industries Co,. Ltd.
Lattin Christopher
Niebling John F.
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