Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package
Reexamination Certificate
2000-03-01
2004-06-08
Pham, Long (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
C257S687000, C257S730000, C257S773000, C257S787000, C257S795000
Reexamination Certificate
active
06747345
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field Of The Invention
The present invention relates generally to microelectronic packaging and, more particularly, to a method and apparatus for applying a protective ring about the perimeter of an exposed die face.
2. Description Of The Related Art
This section is intended to introduce the reader to various aspects of art which may be related to various aspects of the present invention which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present invention. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
Packaging of electrical circuits is a key element in the technological development of any device containing electrical components. Several technologies have been developed to provide a means of mounting these electrical components on a surface such as a printed circuit board (PCB). Fine pitch surface mount (FPT), pin grid array (PGA), and ball grid array (BGA) are examples of leading surface mount technologies.
BGA technology offers several advantages over FPT and PGA. Among the most often cited advantages of BGA are: reduced co-planarity problems, since there are no leads; reduced placement problems; reduced paste printing problems; reduced handling damage; smaller size; better electrical and thermal performance; better package yield; better board assembly yield; higher interconnect density; multi-layer interconnect options; higher IO's for a given footprint; easier extension to multi-chip modules; and faster design-to-production cycle time.
A BGA semiconductor package generally includes a semiconductor chip mounted on the upper surface of a substrate. The semiconductor chip may be electrically coupled to the substrate by bonding wires. The substrate contains conductive routing which allows the signals to pass from the semiconductor chip on the top side of the substrate, through the substrate, and to pads on the underside of the substrate. A plurality of solder balls are deposited and electrically coupled to the pads on the underside of the substrate to be used as input/output terminals for electrically connecting the substrate to a PCB or other external device.
To protect the semiconductor chip and bonding wires from external elements such as moisture, dust, or impact, the semiconductor chip is often encapsulated in a molding compound. To encapsulate the semiconductor chip, vacuum based systems are implemented to inject a molding compound which completely encompasses the chip. Disadvantageously, by encasing the entire semiconductor chip in a molding compound, the overall height of the circuit package will be increased. Further, the current system for encapsulating the semiconductor chip implements vacuum ports to seat the film which is used to separate the molding compound from the packaging system after encapsulation is complete. These vacuum ports may become contaminated with the molding compound which is used to encase the semiconductor chip.
The present invention may address one or more of the problems set forth above.
SUMMARY OF THE INVENTION
Certain aspects commensurate in scope with the disclosed embodiments are set forth below. It should be understood that these aspects are presented merely to provide the reader with a brief summary of certain forms the invention might take and that these aspects are not intended to limit the scope of the invention. Indeed, the invention may encompass a variety of aspects that may not be set forth below.
In accordance with one aspect of the present invention, there is provided a system for molding a circuit package. The system comprises a first support plate, a second support plate, and a cavity plate which is positioned between the first and second support plates during the encapsulation process. The cavity plate has an aperture configured to receive a protruding portion of the circuit package. The circuit package generally contains a semiconductor chip which is attached to a substrate. The semiconductor chip is generally the protruding portion of the circuit package.
In accordance with another aspect of the present invention, there is provided an open-faced circuit package. The circuit package generally contains a semiconductor chip which is attached to a substrate. A molding compound is disposed onto the substrate surface to form a protective ring about the periphery of the semiconductor chip, leaving the top surface of the semiconductor chip void of any molding compound.
In accordance with still another aspect of the present invention, there is provided a method for molding a circuit package. The method comprises the steps of: disposing the circuit package on a cavity plate; disposing the cavity plate on a first support plate; disposing a second support plate on the cavity plate; injecting a molding compound into the cavity plate; separating the second support plate from the cavity plate; separating the cavity plate from the first support plate; and separating the circuit package from the cavity plate.
One advantage of the present invention is that there is no additional height added to the top of the circuit package during the encapsulation process. Further, because the face of the die is left exposed, the circuit package will advantageously dissipate heat rapidly. A second advantage of the present invention is that the apparatus used during the injection process does not require a vacuum system. Therefor, the system may be easier to implement in current fabrication facilities. Also, one problem associated with vacuum-based systems is that the vacuum system often becomes contaminated with molding compound during the injection process. A vacuumless system will not have this problem.
REFERENCES:
patent: 4980019 (1990-12-01), Baerg et al.
patent: 5405255 (1995-04-01), Neu
patent: 5654877 (1997-08-01), Burns
patent: 6048483 (2000-04-01), Miyajima
patent: 6081997 (2000-07-01), Chia et al.
Louie Wai-Sing
Pham Long
LandOfFree
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