Stock material or miscellaneous articles – Nonparticulate element embedded or inlaid in substrate and...
Reexamination Certificate
2000-12-30
2004-07-06
Ahmad, Nasser (Department: 1772)
Stock material or miscellaneous articles
Nonparticulate element embedded or inlaid in substrate and...
C428S114000, C428S138000, C428S172000, C428S195100, C428S209000, C428S210000, C438S016000, C438S975000, C257S797000, C216S019000
Reexamination Certificate
active
06759112
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of semiconductor integrated circuit (IC) manufacturing, and more specifically, to improving the design of an overlay structure.
2. Discussion of Related Art
Many parameters of a semiconductor device must be monitored during fabrication to assure that the device will meet the specifications for performance and reliability at the end of the line. Since device fabrication may involve as many as 30 layers, it is particularly important to measure the overlay of the critical layers to each other. One critical overlay for a microprocessor is polysilicon gate layer to shallow trench isolation layer. Another critical overlay is first metal layer to contact layer.
It is very challenging to measure overlay directly in a product die on a wafer. This is because of the extremely small horizontal and vertical dimensions of the features and the multiple layers of material stacked on the wafer. However, test structures representing any two layers of interest may be placed in the scribelines separating the die. Then, overlay data, collected in accordance with a statistically valid sampling plan, may be analyzed using an appropriate model. The overlay may be partitioned into an orthogonal set of components which correspond to physically meaningful parameters on the step-and-scan tool that exposed the wafer. Such a feedback loop allows the step-and-scan tool to be adjusted to improve overlay on wafers processed later.
As the design groundrules continue to shrink, it becomes increasingly critical to design a robust overlay structure to accommodate the process variations that can introduce considerable noise into an overlay measurement. As an example, gate layer is usually formed from polysilicon that has been deposited by chemical vapor deposition (CVD) and planarized by chemical-mechanical polishing (CMP). These processes affect the thickness, roughness, and graininess of the polysilicon, thus making overlay measurement difficult.
Overlay refers to the relative placement of a subsequent layer with reference to a previous layer. Overlay is generally measured in two orthogonal orientations. The orientations are usually chosen to correspond to the x-axis and the y-axis of the stage of the step-and-scan tool used to expose photoresist on the layers. For illustrative purposes in the following description, the polysilicon gate layer will be chosen as the subsequent or second layer and the shallow trench isolation layer will be chosen as the previous or first layer.
FIG. 1
shows a cross-sectional view of a wafer
5
in one of the two orientations after develop. The substrate
10
is formed from a semiconductor material such as silicon. Then the surface of the substrate
10
is covered with silicon oxide
30
. The outer bars
15
are formed at the first layer from shallow trenches that have been filled with a dielectric material
20
. After depositing a layer of polysilicon
40
over the entire wafer, a coat of photoresist is applied. A step-and-scan tool aligns layer two (on a mask) to layer one (on the wafer) and then exposes the photoresist through the mask to form a latent image of the desired pattern from the mask in the photoresist. The inner bars
45
are formed after developing the photoresist
50
.
Overlay is measured after develop since, if necessary, the photoresist may be removed and re-applied for patterning again before etching is performed. First, the centerline
54
of the inner bars
45
is determined from the midpoint of the distance
52
between the centers of the inner bars. Second, the centerline
14
of the outer bars
15
is determined from the midpoint of the distance
12
between the centers of the outer bars. Finally, the overlay after develop is calculated as the difference
24
between the centerline
54
of the inner bars
45
and the centerline
14
of the outer bars
15
.
FIG. 2
shows a cross-sectional view of a wafer
7
after etch in the same orientation as FIG.
1
. The top of the outer bars
15
is now exposed since the overlying polysilicon layer has been removed by the etch. The inner bars
45
are formed from polysilicon
40
.
Overlay is also measured after etch. Rework of the photoresist is no longer possible, but the etch must be monitored since the pattern in the photoresist has been transferred into the layers of material on the wafer. First, the centerline
55
of the inner bars
46
is determined from the midpoint of the distance
53
between the centers of the inner bars
46
. Second, the centerline
17
of the outer bars
15
is determined from the midpoint of the distance
13
between the centers of the outer bars
15
. Finally, the overlay after etch is calculated as the difference
25
between the centerline
55
of the inner bars
46
and the centerline
17
of the outer bars
15
.
It is preferable to measure post-develop overlay at a layer because rework of the photoresist is still possible. However, data from cross-sectioned wafers reveal that post-etch overlay is a better predictor of overlay in product devices than post-develop overlay. Overlay measurement becomes more consistent after etch because polysilicon has been removed from over the overlay structure. Consequently, it is often necessary to measure overlay after develop and again after etch in order to determine an etch offset. The etch offset is then applied to correct subsequent post-develop measurements. Unfortunately, the etch offset is not very consistent unless results are obtained by measuring the same locations on the same wafers after develop and after etch. Such a procedure is laborious and time consuming. Furthermore, the etch offset must be updated frequently since it will often fluctuate.
REFERENCES:
patent: 3731085 (1973-05-01), Bostrom
patent: 5308682 (1994-05-01), Morikawa
patent: 6368921 (2002-04-01), Hijzen et al.
patent: 6413827 (2002-07-01), Farrar
Chen George
Intel Corporation
Rhee Jane
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