Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
2001-02-05
2004-07-06
Malzahn, David H. (Department: 2124)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
C708S205000
Reexamination Certificate
active
06760738
ABSTRACT:
BACKGROUND
1. Technical Field
The present invention relates generally to a data processing system and, in particular, to a data processing unit including an exponent unit for outputting the number of consecutive bits having the same value as a most significant bit of an operand.
2. Background Description
An exponent unit used in a data processing system, such as a digital signal processor (DSP), outputs the number of consecutive bits having the same value as a most significant bit (MSB) of an operand. An exponent value, which is output from such an exponent unit, is used as shift information for performing a fixed point arithmetic operation or a multiplication/division arithmetic operation, enhancing the operation speed of the data processing system.
For example, if a binary “0.0000011” is expressed with the fixed-point number, left shifting is performed five times. An exponent thereof is a decimal “5”. Using an exponent unit for a fixed point change, an exponent can easily be obtained. That is, an exponent having the same value as a most significant bit is a decimal “6”. And, subtracting “1” from the “6” makes the “5”.
It is understood that as the number of bits of data used in a data processing system for accurate data expression rises, a processing bit width of circuits formed therein must increase. Therefore, if the processing bit width of the data processing system increases, then that of the exponent unit must also increase. This causes increases in hardware area and manufacturing costs.
Therefore, it is an object of the present invention to provide an exponent unit of a data processing system which can process at least double data bits with a minimal addition of hardware.
SUMMARY OF THE INVENTION
To achieve the above and other objects of the present invention, there is provided an exponent unit adapted to receive an operand and to output an exponent of the operand, and a data processing system including the exponent unit. The exponent of the operand output from the exponent unit is equal to the number of consecutive bits of the operand that have the same value as the most significant bit (MSB) of the operand.
According to a first aspect of the invention, there is provided an exponent unit adapted to receive an operand and to output an exponent of the operand The exponent unit includes a detection device adapted to detect a number of consecutive bits of the operand having a same value as a most significant bit (MSB) of the operand, and to output a detection value corresponding thereto. A mantissa and carry control device is adapted to output the detection value as a mantissa signal in at least one of a single precision mode and, when a previous first status bit is set and the MSB is identical to a previous second status bit, in a double precision mode. The mantissa and carry control device is also adapted to generate a carry signal in the double precision mode, when the previous first status bit is set and the MSB is identical to the previous second status bit. An augend control device is adapted to output an exponent of a previous operand as an augend signal. A logic circuit is adapted to set a first status bit and to set a second status bit to a lowest bit of the operand, when all bits of the operand have an identical value. An adder is adapted to add the mantissa signal, the augend signal, and the carry signal to obtain a sum thereof, and to output the sum as the exponent of the operand. The single precision mode and the double precision mode are sequentially generated, and the exponent of the operand is equal to the number of consecutive bits of the operand having the same value as the MSB of the operand.
According to a second aspect of the invention, there is provided a data processing system. The data processing system includes an exponent unit adapted to output an exponent of an operand that is equal to a number of consecutive bits of the operand having a same value as a most significant bit (MSB) of the operand. A status register is adapted to store previous first and second status bits. A decoder is adapted to decode an instruction including the operand, to supply the operand and the previous first and second status bits stored in the status register to the exponent unit when the decoded instruction is an exponent instruction, and to output a mode signal having a first level or a second level depending upon whether the decoded instruction is a single precision exponent instruction or a double precision exponent instruction, respectively. The exponent unit includes first and second latches, a mantissa and carry control device, an augend control device, a logic circuit, and an adder. The first and second latches are adapted to latch the previous first and second status bits supplied from the status register, respectively. The detection device is adapted to detect the number of consecutive bits of the operand having the same value as the MSB, and to output a detection value corresponding thereto. The mantissa and carry control device is adapted to output the detection value as a mantissa signal when the mode signal is at the first level or when the mode signal is at the second level, the previous first status bit is set, and the previous second status bit is identical to the MSB, and to output a carry signal when the mode signal is at the second level, the previous first status bit is set, and the previous second status bit is identical to the MSB. The augend control device is adapted to output an exponent of a previous operand as an augend signal when the mode signal is at the second level. The logic circuit is adapted to set a first status bit and to set a second status bit to a lowest bit of the operand, when all bits of the operand have an identical value. The adder is adapted to add the mantissa signal, the augend signal, and the carry signal to obtain a sum thereof, and to output the sum as the exponent of the operand. The first and second latches are further adapted to retain a latched value for a predetermined time, and the single precision exponent instruction and the double precision exponent instruction are sequentially generated.
These and other aspects, features and advantages of he present invention will become apparent from the following detailed description of preferred embodiments, which is to be read in connection with the accompanying drawings.
REFERENCES:
patent: 5699285 (1997-12-01), Miyanishi et al.
patent: 6154760 (2000-11-01), Sharangpani
patent: 6301594 (2001-10-01), Ahmed
Kim Hong-Kyu
Kim Yang-Ho
F. Chau & Associates LLC
Malzahn David H.
Samsung Electronics Co,. Ltd.
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