Exploiting shortest path for improved network clock...

Details Exploiting shortest path for improved network clock... Exploiting shortest path for improved network clock...

2005-12-06

2005-12-06

Patel, Jay K. (Department: 2637)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S374000, C375S376000, C370S518000

Reexamination Certificate

active

06973152

ABSTRACT:
Apparatus and methods are provided for exploiting the existence of a shortest path between a source device and a destination device by identifying the shortest path and using the signal which has taken the shortest path in preference to delayed transmissions or delayed images of the same signal, thereby improving signal distribution. The present invention provides a processor between a phase-sensitive detector and a low pass filter of a phase locked loop for selecting and driving the PLL primarily from the signal which has taken the shortest path.

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