Expansible FIFO memory for accommodating added memory stages in

Details Expansible FIFO memory for accommodating added memory stages in Expansible FIFO memory for accommodating added memory stages in

1988-09-16

1992-05-26

Gossage, Glenn

Static information storage and retrieval

Read/write circuit

Serial read/write

36523003, G11C 1900, G11C 800

Patent

active

051173956

ABSTRACT:
An expansible FIFO memory device to which additional memory stages having the same internal memory structure may be connected to form a multistage memory of increased memory storage capacity, uses a basic control circuit which is applicable to all of the added memory stages. The respective memory stages are connected in parallel such that only one memory stage is operable at one time instant in performing a data write or a data read operation. As a memory stage is completely filled with data written thereinto or conversely is completely emptied from the readout of data therefrom, the control circuit common to all of the memory stages provides appropriate signals indicative of the full condition of the memory stage in a data write operation and of the empty condition of the memory stage in a data read operation which signals are communicated to the next memory stage for activation thereof in a continuation of the data write or data read operation. Memory capacity of the expansible FIFO memory device may be thereby increased by adding memory stages thereto without complicating the control circuit and increasing the circuit components thereof.

REFERENCES:
patent: 4562435 (1985-12-01), McDonough et al.
patent: 4799198 (1989-01-01), Ogawa
Tunick, "Rich with logic, Memory ICs Hone their Specialties", Electronic Design, Jun. 11, 1987, pp. 77-86.
Pai, FIFO RAM Controller Tackles Deep Data Buffering, Computer Design, Aug. 1, 1986, pp. 109-112.

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