Electrical computers and digital processing systems: processing – Instruction decoding – Predecoding of instruction component
Reexamination Certificate
1998-10-02
2001-05-29
Donaghue, Larry D. (Department: 2154)
Electrical computers and digital processing systems: processing
Instruction decoding
Predecoding of instruction component
C712S210000, C712S205000
Reexamination Certificate
active
06240506
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to microprocessors configured to execute variable-length instruction sets, and in particular, instruction sets having address and operand size prefixes.
2. Description of the Relevant Art
The number of software applications written for the x86 instruction set is immense. As a result, despite the introduction of newer and more advanced instruction sets, microprocessor designers have continued to design microprocessors capable of executing the x86 instruction set.
The x86 instruction set is relatively complex and is characterized by a plurality of variable-length instructions. A generic format illustrative of the x86 instruction set is shown in FIG.
1
. As the figure illustrates, an x86 instruction consists of from one to five optional prefix bytes
102
, followed by an operation code (opcode) field
104
, an optional addressing mode (Mod R/M) byte
106
, an optional scale-index-base (SIB) byte
108
, an optional displacement field
110
, and an optional immediate data field
112
.
The opcode field
104
defines the basic operation for a particular instruction. The default operation of a particular opcode may be modified by one or more of the optional prefix bytes
102
. For example, one of prefix bytes
102
may be used to override the default segment used in memory addressing or to instruct the processor to repeat a string operation a number of times.
Two prefix bytes are of particular importance. A prefix byte of 66(hex) represents the OPSIZ prefix, which reverses the default the operand size for an instruction. A prefix byte of 67(hex) represents the ADRSIZ prefix, which reverses the default address size for an instruction. The default operand and address size of an instruction is determined by a default bit within the instruction's segment descriptor. If the default bit is set, then the default address and operand size is 32-bits. A prefix of 66(hex) or 67(hex) will override a set default bit, thereby allowing an instruction to use a 16-bit opcode or address, respectively. Similarly, if the default bit is not set, then the default address and operand size is 16-bits. A prefix of 66(hex) or 67(hex) will then override the unasserted default bit and allow the instruction following the prefix to use a 32-bit opcode or address, respectively. Thus, not only does the length of an x86 instruction depend upon how many prefix bytes precede the instruction, but also upon the value of the default bit in the instruction's segment descriptor and the presence of specific prefix bytes 66(hex) and 67(hex).
The opcode field
104
follows prefix bytes
102
(if present) and may be one or two bytes in length. The addressing mode (Mod R/M) byte
106
specifies the registers used as well as memory addressing modes. The scale-index-base (SIB) byte
108
is used only in 32-bit base-relative addressing using scale and index factors. A base field within SIB byte
108
specifies which register contains the base value for the address calculation, and an index field within SIB byte
108
specifies which register contains the index value. A scale field within SIB byte
108
specifies the power of two by which the index value will be multiplied before being added, along with any displacement, to the base value. The next instruction field is a displacement field
110
, which is optional and may be from one to four bytes in length. Displacement field
110
contains a constant used in address calculations. The optional immediate field
112
, which may also be from one to four bytes in length, contains a constant used as an instruction operand. The shortest x86 instructions are only one byte long, and comprise a single opcode byte. The 80286 sets a maximum length for an instruction at 10 bytes, while the 80386 and 80486 both allow instruction lengths of up to 15 bytes.
The complexity of the x86 instruction set poses many difficulties in implementing high performance x86 -compatible microprocessors. In particular, the variable length of x86 instructions, the nature of the prefix bytes, and reliance upon the segment descriptor makes scanning, aligning, and decoding instructions difficult. Scanning refers to reading a group of instruction bytes (either from an instruction cache within the microprocessor or from an external memory) and determining the boundaries of instructions contained therein. Alignment refers to the process of masking off undesired instruction bytes and shifting the desired instruction bytes so that the first bit of the desired instruction is in a desired position. Decoding instructions typically involves identifying each field within a particular instruction, e.g., the opcode and operand fields. Decoding typically takes place after the instruction has been fetched from the instruction cache, scanned, and aligned.
One method for aligning instructions involves generating a number of predecode bits for each instruction byte read from main memory. The predecode bits provide information about the instruction byte they are associated with. For example, an asserted predecode start bit indicates that the associated instruction byte is the first byte of an instruction. Similarly, an asserted predecode end bit indicates that the associated instruction byte is the last byte of an instruction. Once the predecode bits for a particular instruction byte are calculated, they are stored together with the instruction byte in an instruction cache. When a “fetch” is performed, i.e., a number of instruction bytes are read from the instruction cache, the associated start and end bits are also read. The start and end bits may then be used to generate valid masks for the individual instructions with the fetch. A valid mask is a series of bits in which each bit corresponds to a particular instruction byte. Valid mask bits associated with the first byte of an instruction, the last byte of the instruction, and all bytes between the first and last bytes of the instruction are asserted. All other valid mask bits are not asserted.
Turning now to
FIG. 2
, an exemplary valid mask is shown. The figure illustrates a portion of a fetch block
120
and its associated start and end bits
122
and
124
. Assuming a valid mask
126
for instruction B
128
is to be generated, start and end bits
122
and
124
would be used to generate the mask. Valid mask
126
could then be used to mask off all bytes within fetch
120
that are not part of instruction B
128
. Once the boundaries of an instruction have been determined, alignment and decoding may be performed.
Unfortunately, the tasks of scanning and aligning x86 instructions typically require a number of cascaded levels of logic. Thus, scanning and alignment may require a significant amount of time and, when added to the time required to perform decoding, may create a significant delay before any instructions are available to the functional stages of the microprocessor's pipeline. As microprocessors increase the number of instructions they are able to execute per clock cycle, slow instruction scanning and alignment may become a performance limiting factor. Therefore, a mechanism for reducing the complexity and time required for instruction scanning and alignment is needed.
SUMMARY OF THE INVENTION
The problems outlined above may in part be solved by a microprocessor configured to receive instructions having varying address and operand sizes and then predecode them into a single fixed-sized format. During predecode, the microprocessor may be configured to detect prefix bytes that override an instruction'default address and operand length, thus allowing the instructions to be “recast” into a single fixed size format. Advantageously, in some embodiments this may simplify instruction scanning and alignment.
In one embodiment, the microprocessor may comprise a predecode unit and an instruction cache. The predecode unit may be configured to receive instruction bytes from a main memory subsystem. The predecode unit may then be configured to detect instructions having prefix bytes that
Advanced Micro Devices , Inc.
Christen Dan R.
Conley & Rose & Tayon P.C.
Donaghue Larry D.
LandOfFree
Expanding instructions with variable-length operands to a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Expanding instructions with variable-length operands to a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Expanding instructions with variable-length operands to a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2572006