Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2002-11-06
2004-08-17
Lam, David (Department: 2818)
Static information storage and retrieval
Addressing
Sync/clocking
C365S189050, C365S194000
Reexamination Certificate
active
06778464
ABSTRACT:
RELATED APPLICATIONS
This application claims priority to Korean Patent Application No.
2001-69227
, filed on Nov. 7, 2001, the contents of which are herein incorporated by reference in their entirety.
FIELD OF THE INVENTION
The present invention relates to a synchronous semiconductor memory, and more particularly, to a synchronous semiconductor memory device having a wave pipeline and a wave pipeline control method.
BACKGROUND OF THE INVENTION
In digital systems, including a synchronous semiconductor memory device that operates synchronized with a system clock, latency typically increases as the frequency of the system clock increases. In response to the increasing latency, a wave pipeline has been used to control the latency in the synchronous semiconductor memory device. Latency refers to the number of cycles of the system clock that are needed to perform a read operation. Latency is typically measured as the time from when a read command is sent to a synchronous semiconductor memory device until a time when a first data item is output.
FIG. 1
is a diagram of a Double Data Rate (DDR) synchronous dynamic random access memory (DRAM) having a prior art wave pipeline structure. In the DRAM of
FIG. 1
, the latency is N cycles (N is an integer).
FIG. 2
is a timing diagram of data outputs of the DDR synchronous DRAM of FIG.
1
.
Because the latency is N, a stack unit
14
has N stack registers or storage units, and a stack counter
17
generates a signal (SC) that is activated with a period of N cycles of the system clock. The stack unit
14
stores data (DATA) that is read from a memory cell array
10
for N cycles of the system clock (CLK) in response to the output signal (SC) of the stack counter
17
. When a read command (READ) is input, data (DATA) is read from the memory cell array
10
through a sense amplifier
11
, a column selection transistor
12
, and a latch
13
.
Data stored in the stack unit
14
is sequentially output through a parallel to serial converter
15
and an output buffer
16
. The parallel to serial converter
15
is controlled by a clock that is obtained when a latency control circuit
19
delays a control clock (CLKDQ) generated in a delay synchronization loop (DLL)
18
for a predetermined time.
However, when the synchronous DRAM shown in
FIG. 1
operates at a low frequency, that is, when the frequency of the system (CLK) is a low frequency, failure may occur because data is not stably latched at the falling edge of the system clock (CLK) as shown in the timing diagram of FIG.
3
. For example, when Ta denotes a time for stably storing a first data item
00
in the stack unit
14
after a read command (READ) is input, and Tb denotes a time for aligning the data to the falling edge of the system clock (CLK) from the rising edge of the control clock (CLKDQ) generated in the DLL
18
to the falling edge of the system clock (CLK), if Ta+Tb is less than TCC/2, a failure occurs. TCC denotes the cycle or period of the system clock (CLK).
This failure of a low frequency operation can be prevented by increasing the number of stacks in the stack unit
14
by 1. For example, if the number of stacks in the stack unit
14
is N+1, the stack unit
14
stores data (DATA) for N+1 cycles of the system clock (CLK), and accordingly a time for stably latching the first data item
00
after the read command (READ) is input increases to Ta+TCC. Therefore, Ta+TCC+Tb becomes greater than TCC/2 and the failure of a low frequency operation can be prevented.
Thus, in the synchronous DRAM shown in
FIG. 1
, by increasing the number of stacks of the stack unit
14
by
1
, the failure of a low frequency operation can be prevented. However, as a result of the increase in the number of stacks, the characteristics of a high frequency may be degraded.
SUMMARY OF THE INVENTION
Embodiments of the present invention provide a synchronous semiconductor memory device that operates synchronized with an operation clock. The synchronous semiconductor memory device has a latency N, where N is an integer and includes a memory cell array, a stack unit having N storage units and a frequency detector configured to determine a relationship of a frequency of the operation clock with reference to a predetermined frequency so as to provide an output signal based on the relationship of the frequency of the operation clock to the predetermined frequency. A control circuit is configured to control the stack unit in response to the output signal of the frequency detector. The control circuit latches data read from the memory cell array and controls the stack unit so that the latched data is stored from a clock cycle when a read command is sent until an N-th clock cycle after the read command is sent if the frequency of the operation clock is greater than the predetermined frequency and delays the latched data for one clock cycle and controls the stack unit so that the delayed data is stored from one clock cycle after the read command is sent until an N+1 clock cycle after the read command is sent.
In further embodiments of the present invention, the frequency detector includes a first latch that latches a reference signal in response to a first edge of the operation clock and a second latch that latches the reference signal in response to a second edge of the operation clock. A first delay unit that delays the output signal of the first latch for a first delay time and a second delay unit that delays the output signal of the first delay unit for a second delay time. A third latch latches an output signal of the second latch in response to a first edge of an output signal of the second delay unit and outputs the latched value as the output signal of the frequency detector. In particular embodiments of the present invention, the first edge of the operation clock is a rising edge of the operation clock, the second edge of the operation clock is a falling edge of the operation clock and the first edge of the output signal of the second delay unit is a rising edge of the output signal of the second delay unit.
In still further embodiments of the present invention, the predetermined frequency has a period of twice a sum of the delay of the first delay unit and the delay of the second delay unit. For example, the first delay time may be a time for the stack unit to stably store a first data item of the latched data after the read command is sent. The second delay time may be a time from the rising edge of a control clock generated in a delay synchronization loop in the synchronous semiconductor memory device to a falling edge of the operation clock.
In additional embodiments of the present invention, the predetermined frequency has a period of twice a sum of a time for the stack unit to stably store a first data item of the latched data after the read command is sent and a time from the rising edge of a control clock generated in a delay synchronization loop in the synchronous semiconductor memory device to a falling edge of the operation clock.
In yet other embodiments of the present invention, the control circuit includes a first latch that latches internal data read from the memory cell array in response to a first control signal and a second latch that latches data latched by the first latch in response to a second control signal, and outputs the latched data as the delayed data. A first selector selects one of the data latched by the first latch and the delayed data in response to the output signal of the frequency detector, and outputs the selected data to the stack unit. A second selector selects one of the first control signal and the second control signal in response to the output signal of the frequency detector. A stack counter counts pulses of the output signal of the second selector and outputs an output signal to the stack unit based on the counted pulses. In certain embodiments, the first control signal is a signal having pulses activated at every cycle from a clock cycle when the read command is sent until an N-th clock cycle after the read command is sent
Lam David
Myers Bigel Sibley & Sajovec P.A.
Samsung Electronics Co,. Ltd.
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