Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-08-12
2001-10-16
Everhart, Caridad (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S555000, C438S650000, C438S649000
Reexamination Certificate
active
06303492
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to the manufacture of integrated circuits and, more particularly, to a method of forming electrical contacts within an integrated circuit.
2. Background of the Related Art
Common to virtually all microelectronic or semiconductor fabrication processes is the need to form conductive paths between different circuit elements that have been fabricated in a die. Contacts and vias are customarily used to interconnect these elements. Contacts and vias are typically fabricated by forming holes between one layer and another and by filling these holes with a conductive material to form a conductive path.
Prior art techniques used to create contacts typically include the following steps: (1) forming a contact hole; (2) implanting a dopant into the bottom of the contact hole; (3) depositing a barrier material, such as titanium, for example, to coat the contact hole's surfaces; (4) annealing the structure; and (5) filling the contact hole with a suitable conductive material. An anisotropic procedure is typically used to etch a contact hole over a selected region of the semiconductor substrate. The contact hole provides an opening through one or several of the semiconductor's insulating layers to the active region or to another conducting layer, such as polysilicon or tungsten silicide. Thus, the contact hole determines the shape and position of the electrical contact that will be formed later in the procedure.
As component packing densities increase, the potential for contact-to-substrate leakage also increases. Here, contact-to-substrate leakage refers to current leakage through the contact fill material to the underlying semiconductor substrate. Two well-known causes of increased contact-to-substrate leakage are: (1) misalignment between the contact hole and the targeted underlying region of the semiconductor and (2) excessive etching during contact hole formation. Both of these problems may lead to increased current leakage and, as a result, reduced circuit performance.
A defect in the placement or depth of a contact hole may impair a contact's performance. Misaligned, over-sized, and over-etched contact holes frequently cause leakage current between the contacts and other structures, such as the underlying substrate. As the density of integrated circuits continues to increase, as it has in the fabrication of static random access memories (SRAMs) and dynamic random access memories (DRAMs), alignment problems have become more troublesome.
The present invention may address one or more of the problems set forth above.
SUMMARY OF THE INVENTION
Certain aspects commensurate in scope with the originally claimed invention are set forth below. It should be understood that these aspects are presented merely to provide the reader with a brief summary of certain forms the invention might take and that these aspects are not intended to limit the scope of the invention. Indeed, the invention may encompass a variety of aspects that may not be set forth below.
In accordance with one aspect of the present invention there is provided a method of forming a contact in an integrated circuit. The method includes the steps of: (a) forming an active region in a silicon substrate; (b) forming a layer of dielectric material over the active region in the substrate; (c) forming a contact hole in the layer of dielectric material to expose at least a portion of the active region in the substrate, the contact hole having side walls and a longitudinal axis, and the exposed portion of the substrate forming a bottom surface of the contact hole; (d) implanting a dopant at a positive angle Lo relative to the longitudinal axis to form a plug implantation region in the bottom surface of the contact hole which extends into the substrate beneath the dielectric material adjacent the side walls; (e) depositing a layer of titanium within the contact hole, the layer of titanium coating the side walls and the bottom surface; (f) depositing a layer of titanium nitride over the layer of titanium; (g) annealing the substrate to form a layer of titanium silicide on the bottom surface, the layer of titanium silicide being completely contained within the plug implantation region; and (h) filling the contact hole with a conductive material.
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Hagen Kenneth N.
Ireland Philip J.
Prall Kirk D.
Rhodes Howard E.
Everhart Caridad
Fletcher Yoder & Van Someren
Micro)n Technology, Inc.
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