Electrical computers and digital data processing systems: input/ – Intrasystem connection – Protocol
Reexamination Certificate
1999-08-05
2004-05-04
Vo, Tim (Department: 2781)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Protocol
C710S106000, C370S366000
Reexamination Certificate
active
06732206
ABSTRACT:
BACKGROUND
(1) Field of the Invention
The invention relates to bus system. More specifically, the invention relates to traffic queuing and prioritization in high throughput bus systems.
(2) Background
A number of buses exist which provide for addressing of bus entities. Many of these buses have a relatively small number and therefore, low granularity for the number of entities that can be addressed on the bus. One existing bussing protocol that falls within this genre is the Utopia 2 protocol, as set forth in the Utopia Level 2, V 1.0 June 1995 (Utopia 2). Utopia 2 and subsequent revisions are referred to generically herein as “Utopia” protocols.
Utopia 2 was designed to permit an asynchronous transfer mode (ATM) layer to communicate with a group of Multi-PHYs (MPHYs). Utopia 2 provides for only thirty unique addresses. Thus, the number of bus entities is limited to thirty. This may not be problematic, where each device supplying or consuming data from the Utopia bus provides only a single outbound port from the bus to the outside world. However, when each physical device coupled to the bus has multiple ports, addressing using the bus supported addressing system becomes difficult or impossible.
BRIEF SUMMARY OF THE INVENTION
A system of expanding addressing in an addressing constrained environment is disclosed. A bus that defines a limited number of addresses couples together a master and a plurality of slaves. When each slave has multiple possible target ports, a maximum granularity provided by the addressing may be exceeded. By using a portion of a transmission header as an internal address, the: maximum addressing may be expanded to greater granularity. The internal address is then translated in the slave to recover the external address in the header.
REFERENCES:
patent: 5848068 (1998-12-01), Daniel et al.
patent: 5878045 (1999-03-01), Timbs
patent: 5923660 (1999-07-01), Shemla et al.
patent: 6269096 (2001-07-01), Hann et al.
patent: 6418492 (2002-07-01), Papa et al.
patent: 6487203 (2002-11-01), Chung et al.
Jensen John Neil
Muliadi Harun
Accelerated Networks
Blakely , Sokoloff, Taylor & Zafman LLP
Vo Tim
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