Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2000-11-02
2004-02-03
Lefkowitz, Sumati (Department: 2189)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C326S030000
Reexamination Certificate
active
06687780
ABSTRACT:
The present invention relates to an expandable slave device system in a computer system, and in particular to an expandable slave device system using a global bus and multiple subsystem buses.
BACKGROUND OF THE INVENTION
The size of computer application programs is ever-increasing; therefore, the amount of memory needed to handle the application programs is also increasing. To reduce the execution time of the application programs, larger amounts of memory, such as semi-conductor random access memory (RAM) are added to computer systems.
In
FIG. 1
, a bus system is a chip-to-chip electronic communications system that connects one or more slave devices
42
to a master device
44
through shared communication lines
46
, called a bus. Typically, the slave devices
42
are memory devices. In a typical memory system
50
, the bus
46
interconnects a memory control master device (M)
44
and memory devices (D)
42
. The bus
46
is a bi-directional data bus having many signal lines
54
-
1
to
54
-m. In a bidirectional data bus, the memory control master device
44
transmits information on the signal lines
54
to the memory devices
42
, and the memory devices transmit information back to the memory control master device
44
on the signal lines
54
. The data bus
46
has a loaded bus impedance of Z
L
. For reliable operation at the loaded bus impedance Z
L
at a given frequency, the memory system
50
has a maximum predetermined number (from one to N) of memory devices
42
connected to the data bus
52
. The bi-directional data bus
46
has many bus signal lines
54
. One end of each bus signal line
54
terminates at an I/O pin
56
-M on the master device
44
; the other end of each bus signal line terminates at a resistive terminator (T)
60
. The impedance or resistance of the resistive terminator
60
matches the loaded bus impedance Z
L
to minimize reflections by absorbing signals transmitted on the bus signal line
54
. The opposite end of each terminator
60
connects to a termination voltage V
T
which provides an AC ground and sets the DC termination voltage of the bus signal line
54
. Because the voltage of the bus signal lines
54
is pulled-up to the value of the termination voltage V
T
, the termination voltage V
T
represents a state of a logical data signal, such as a logical zero, for digital signals transmitted on the bus signal lines
58
. Another state of the logical data signal, such as a logical one, is represented by a voltage that is proportional to an amount of current that flows through the resistive terminator
60
.
Each signal line connects to a write buffer
62
and a read buffer
63
in the master device
44
. The read buffer
63
receives data signals from its respective signal line. The write buffer
62
has a drive circuit that drives data signals onto its respective signal line of the bus
46
.
When driving a logical one, the drive circuit of the write buffer
62
causes current to flow through the resistive terminator
60
. Switched current sources, such as open drain NMOS devices, can be used as drive circuits in either the master device
44
and the memory devices
42
. The drive circuit generates a logical zero state by not providing a path for current to flow through the resistive terminator T
60
to ground. The drive circuit generates a logical one state by providing a path for current to flow through the resistive terminator
60
to ground. In a binary system, a logical zero is represented by the termination voltage V
T
, which will also be referred to as V
Hi
; and, a logical one is represented by a low voltage V
Lo
in accordance with relationship one as follows:
V
Lo
=(
V
T
−IoZ
L
). (1)
The current Io is the nominal amount of current sunk by an active drive circuit when driving a logical one.
This signaling scheme has two benefits. First, the drive circuit does not consume power when driving one of the logical states—the logical zero state V
Hi
. Second, the drive circuit provides a high output impedance to the bus signal lines
54
, which minimizes the amount of energy lost as the signals propagate, past the memory devices
42
, towards the resistive terminator
60
at the ends of the data bus
46
. At the master device
44
, the input impedance is equal to the full loaded impedance Z
L
of the bus signal line
54
. When transmitting signals, the master device
44
generates full-swing signals having a voltage difference V
Swing
equal to the difference between the voltages representing the logical zero and logical one states in accordance with relationship two as follows:
V
swing
=(
V
Hi
−V
Lo
). (2)
The signals transmitted by the master device
44
propagate down the bus signal line
54
, past the memory devices
42
, and terminate at the resistive terminator
60
. The conductor between the bus signal line
54
and an I/O pin
56
of the memory device
42
is referred to as a stub. As long as the I/O pins
56
-D of the memory devices
42
form short stubs and present a high input impedance, the signals lose little energy and produce minimal parasitic reflections as the signals travel down the bus signal line. Stubs are considered to be short if their electrical lengths are shorter than the rise and/or fall times of the signals. The electrical length refers to the amount of time for a signal to propagate from one end of the stub to the other. The physical length of the stub is directly proportional to the electrical length of the stub.
When a memory device
42
transmits to the master device
44
, although connected to a single bus signal line
54
, each drive circuit in the memory device
42
effectively “sees” two lines—one line towards the master
44
and one line towards the resistive terminator
60
. Each line has a net impedance equal to one-half of the full loaded impedance Z
L
of the bus signal lines
54
(½Z
L
). Assuming that the drive circuits in the memory devices
42
also sink an amount of current equal to Io, the signals that emerge from the memory device I/O pins
56
-D split at the bus signal line
54
with half the signal voltage traveling toward the master
102
and half toward the resistive terminators
60
. The half-swing signals that travel toward the resistive terminators
60
pass by the other memory devices
42
and are absorbed by the resistive terminators
60
. The half-swing signals that travel toward the master device
44
pass by other memory devices
42
and encounter an open circuit at the end of the bus signal line
54
at the master device I/O pin
56
-M. The open circuit causes the signals from the memory device
42
to reflect back down the bus signal lines
54
towards the resistive terminator
60
which doubles the voltage at the I/O pin of the master device
56
-M. Although only half of the voltage (i.e. ½V
Swing
) was transmitted towards the master device
44
, the master device
44
still receives a full swing signal V
Swing
at its I/O pins
56
-M because of the reflection, provided that the bus signal lines
54
terminate in a high impedance (i.e., an open circuit) at the master device
44
. The other memory devices
42
in the memory system
50
will see half-amplitude signals pass their I/O pins
56
-D at each of two different times. As a result, these half-amplitude signals cannot be reliably detected by the other memory devices
42
. Since a memory device
42
transmits data to the master device
44
and not to another memory device
42
, this result is acceptable. Regardless of which memory device
42
in the memory system
50
is transmitting, a full swing signal V
Swing
appears at the input of the intended receiving device.
FIG. 2
shows a diagram of the structure and electrical properties of an exemplary bus signal line
54
of the prior art memory system
50
of FIG.
1
. The portion of the bus signal line
54
that connects to the memory devices
42
forms a repetitive structure of signal line segments
64
and memory devices
42
as shown. Each signal line segment
64
can be modeled as a transmission line of
Barth Richard M.
Donnelly Kevin S.
Garlepp Bruno W.
Garrett, Jr. Billy W.
Gasbarro James A.
Lefkowitz Sumati
Pennie & Edmonds LLP
Rambus Inc.
Williams Gary S.
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