Execution of a loop instructing in a loop pipeline after detecti

Details Execution of a loop instructing in a loop pipeline after detecti Execution of a loop instructing in a loop pipeline after detecti

1997-09-12

2000-06-13

Follansbee, John A.

Electrical computers and digital processing systems: processing

Processing control

Branching

712213, 712 23, G06F 900

Patent

active

060761598

ABSTRACT:
A data processor is disclosed which comprises a first pipeline for decoding and executing data instructions, a second pipeline for decoding and executing address instructions, a unit for issuing multiple instructions to the pipelines, a first set of registers being coupled with the first pipeline, and a second set of registers being coupled with the second pipeline, wherein first and second pipeline process data in parallel.

REFERENCES:
patent: 4967339 (1990-10-01), Fukumaru et al.
patent: 5163139 (1992-11-01), Haigh et al.
patent: 5404469 (1995-04-01), Chung et al.
patent: 5546593 (1996-08-01), Kimura et al.
patent: 5560028 (1996-09-01), Sachs et al.
Love, Carl E. et al., "An Investigation of Static Versus Dynamic Scheduling", CH2887-8/90/0000/0192, 1990 IEEE 192-201.

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