Executing partial-width packed data instructions

Details Executing partial-width packed data instructions Executing partial-width packed data instructions

2005-11-29

2005-11-29

Coleman, Eric (Department: 2183)

Electrical computers and digital processing systems: processing

Processing architecture

Array processor

C708S493000, C712S221000

Reexamination Certificate

active

06970994

ABSTRACT:
A method and apparatus for executing partial-width packed data instructions are discussed. The processor may include a plurality of registers, a register renaming unit, a decoder, and a partial-width execution unit. The register renaming unit provides an architectural register file to store packed data operands each of which include a plurality of data elements. The decoder is to decode a first and second set of instructions that each specify one or more registers in the architectural register file. The first set of instructions specify operations to be performed on all of the data elements stored in the one or more specified registers. In contrast, the second set of instructions specify operations to be performed on only a subset of the data elements. The partial-width execution unit is to execute operations specified by either of the first or the second set of instructions.

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