Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
2008-05-13
2008-05-13
Nguyen, Hiep T. (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
Reexamination Certificate
active
11054447
ABSTRACT:
Memory modules are designed with multiple write buffers utilized to temporarily hold write data. “Write-to-buffer” operations moves write data from the memory controller to the write buffers while the memory module is busy processing read operations. Then, address-only “write” commands are later issued to write the buffered write data to the memory device. The write commands targeting idle DIMMs are issued in sequence ahead of writes targeting busy DIMMs (or soon to be busy). Moving the data via a background write-to-buffer operation increases the efficiency of the common write data channel and allows the write data bus to reach maximum bandwidth during periods of heavy read activity. The actual write operations, deferred to periods of when the negative affects of the write can be completely/mostly hidden. In periods of light read activity or when there are no reads pending, buffering data in the memory module enables the buffered data to be written in parallel across multiple memory modules simultaneously.
REFERENCES:
patent: 5590299 (1996-12-01), Bennett
patent: 6807609 (2004-10-01), Lemmon et al.
Brittain Mark Andrew
Maule Warren Edward
Morrison Gary Alan
Stuecheli Jeffrey Adam
Dillon & Yudell LLP
Gerhardt Diana R.
Nguyen Hiep T.
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