Excluding a toggle bit from the range of cacheable addresses...

Details Excluding a toggle bit from the range of cacheable addresses... Excluding a toggle bit from the range of cacheable addresses...

2008-03-18

2008-03-18

Verbrugge, Kevin (Department: 2189)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S103000, C711S118000

Reexamination Certificate

active

11321879

ABSTRACT:
In a method and arrangement for manipulation of the contents of a data memory with which a processing device can be connected to manipulate (in at least one manipulation step at least one first memory range of the data memory, the processing device monitors a monitoring range of the first memory range, the state progression of which allowing the conclusion of the manipulation of the first memory range to be detected. A processing device with a buffer is used, into which buffer the data are read from the data memory. A sub-range of the data memory is established as a first exclusion range of the data memory. The first exclusion range not being read into the buffer. The first exclusion range is established in an establishing step preceding the manipulation step. The exclusion range includes the monitoring range.

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patent: WO 03/027828 (2003-04-01), None

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