Exchanging data and clock lines on multiple format data buses

Details Exchanging data and clock lines on multiple format data buses Exchanging data and clock lines on multiple format data buses

1992-09-18

1994-12-27

Olms, Douglas W.

Communications: electrical

Continuously variable indicating

With meter reading

371 82, H04Q 100

Patent

active

053769287

ABSTRACT:
A bus-controlled signal processing system includes a serial data bus having first and second bus lines for coupling various slave processors to a master control processor. The slave devices require more than one data bus protocol. Each slave device has a bus clock terminal and a bus data terminal. The slave devices dedicated to one protocol have their clock terminals connected to the first bus line and their data terminals connected to the second bus line. The slave devices dedicated to the other protocol have their data terminals connected to the first bus line and their clock terminals connected to the second bus line. The control processor changes the protocol being used to generate bus transmissions as required, and changes the function of the two bus lines when switching between bus protocols to prevent certain bus conflict conditions from occurring.

REFERENCES:
patent: 4574377 (1986-03-01), Miyazaki et al.
patent: 4792950 (1988-12-01), Volk et al.
patent: 4827471 (1989-05-01), Geiger et al.
patent: 5146453 (1992-09-01), Nagler et al.
Philips, "I2C bus in consumer applications" pp. 1-8 (1983).
Intermetall Semiconductors ITT, "Digit 2000 VLSI Digital TV System" p. 17 (1983).

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