Excess energy protection device

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Details

357 2314, 357 41, H01L 2978, H01L 2702

Patent

active

048210960

ABSTRACT:
A device for protecting semiconductor devices during excess energy events. The device uses p-MOS field effect transistors in a common n-well with a common gate configuration. An input is coupled to the source of a first p-type transistor and to the n-well. The first transistor is coupled through a series resistor to a second p-MOS transistor. The drains of each transistor are coupled to ground and gate aided breakdown reduces the voltage at which breakdown occurs.

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