Exception types within a secure processing system

Details Exception types within a secure processing system Exception types within a secure processing system

2003-11-17

2010-02-09

Moazzami, Nasser G (Department: 2436)

Electrical computers and digital processing systems: virtual mac

Task management or control

C726S026000, C726S027000, C713S164000, C713S166000, C713S193000, C712S244000, C711S163000, C710S261000, C710S269000

Reexamination Certificate

active

07661105

ABSTRACT:
An apparatus for processing data includes a processor operable in a plurality modes including at least one secure mode being a mode in a secure domain and at least one non-secure mode being a mode in a non-secure domain. When the processor is executing a program in a secure mode the program has access to secure data which is not accessible when the processor is operating in a non-secure mode. The processor is responsive to one or more exception conditions for triggering exception processing using an exception handler. The processor is operable to select the exception handler from among a plurality of possible exception handlers in dependence upon whether the processor is operating in the secure domain or the non-secure domain.

REFERENCES:
patent: 4825358 (1989-04-01), Letwin
patent: 5386552 (1995-01-01), Garney
patent: 5479616 (1995-12-01), Garibay et al.
patent: 5561788 (1996-10-01), Letwin
patent: 5684948 (1997-11-01), Johnson et al.
patent: 5745770 (1998-04-01), Thangadurai et al.
patent: 5826084 (1998-10-01), Brooks et al.
patent: 5974440 (1999-10-01), Brooks et al.
patent: 5978910 (1999-11-01), Slavenburg
patent: 6363463 (2002-03-01), Mattison
patent: 6604123 (2003-08-01), Bruno et al.
patent: 6742065 (2004-05-01), Suh
patent: 7117284 (2006-10-01), Watt et al.
patent: 7124274 (2006-10-01), Watt et al.
patent: 7165135 (2007-01-01), Christie et al.
patent: 7171539 (2007-01-01), Mansell et al.
patent: 7237081 (2007-06-01), Dahan et al.
patent: 7305712 (2007-12-01), Watt et al.
patent: 7370193 (2008-05-01), Shao et al.
patent: 2001/0008015 (2001-07-01), Vu et al.
patent: 2003/0031235 (2003-02-01), Kim et al.
patent: 2003/0126520 (2003-07-01), Knight
patent: 2003/0140205 (2003-07-01), Dahan et al.
patent: 2003/0140244 (2003-07-01), Dahan et al.
patent: 2003/0140245 (2003-07-01), Dahan et al.
patent: 2004/0139346 (2004-07-01), Watt et al.
patent: 2004/0153672 (2004-08-01), Watt et al.
patent: 2004/0187117 (2004-09-01), Orion et al.
patent: 1054322 (2000-11-01), None
patent: 1162536 (2001-12-01), None
patent: 60-225943 (1985-11-01), None
patent: 1-93830 (1989-04-01), None
patent: 10-69393 (1998-03-01), None
patent: 2001-175486 (2001-06-01), None
patent: 2002-501248 (2002-01-01), None
patent: 2002-182560 (2002-06-01), None
patent: 2004-531788 (2004-10-01), None
patent: WO 90/0595 (1990-05-01), None
patent: WO 99/38073 (1999-07-01), None
Edgar Auslander et al, Security Paradigm for Mobile Terminals, John Wiley & Sons Ltd, 2002, pp. 201-215.
Trusted Computing Group (TCG), Main Specification Version 1.1a, Sep. 1, 2001, pp. i-x and 1-322.
ARM710 Data Sheet, Dec. 1994, pp. 1-130.
A. Chien et al, “Safe and Protected Execution for the Morph/AMRM Reconfigurable Processor”Field-Programmable Custom Computing Machines, Apr. 1999, pp. 209-221.
Related U.S. Appl. No. 10/714,518, filed Nov. 17, 2003, Watt et al.
Related U.S. Appl. No. 10/714,563, filed Nov. 17, 2003, Watt et al.
Related U.S. Appl. No. 10/714,178, filed Nov. 17, 2003, Orion et al.
Related U.S. Appl. No. 10/713,456, filed Nov. 17, 2003, Orion et al.
Related U.S. Appl. No. 10/714,521, filed Nov. 17, 2003, Belnet et al.
Related U.S. Appl. No. 10/714,561, filed Nov. 17, 2003, Watt et al.
Related U.S. Appl. No. 10/714,520, filed Nov. 17, 2003, Belnet et al.
Related U.S. Appl. No. 10/714,483, filed Nov. 17, 2003, Watt et al.
Related U.S. Appl. No. 10/714,516, filed Nov. 17, 2003, Watt et al.
Related U.S. Appl. No. 10/714,484, filed Nov. 17, 2003, Watt et al.
Related U.S. Appl. No. 10/714,562, filed Nov. 17, 2003, Watt et al.
Related U.S. Appl. No. 10/714,560, filed Nov. 17, 2003, Watt et al.
Related U.S. Appl. No. 10/714,565, filed Nov. 17, 2003, Watt et al.
Related U.S. Appl. No. 10/714,482, filed Nov. 17, 2003, Watt et al.
Related U.S. Appl. No. 10/713,454, filed Nov. 17, 2003, Mansell et al.
Related U.S. Appl. No. 10/713,303, filed Nov. 17, 2003, Symes.
Related U.S. Appl. No. 10/714,480, filed Nov. 17, 2003, Watt et al.
Related U.S. Appl. No. 10/714,481, filed Nov. 17, 2003, Watt.
Japanese Office Action mailed Apr. 3, 2009 for JP Application 2004-570294.

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