Exception handling using an exception pipeline in a...

Details Exception handling using an exception pipeline in a... Exception handling using an exception pipeline in a...

2000-12-15

2004-11-23

Chan, Eddie (Department: 2183)

Electrical computers and digital processing systems: processing

Processing control

Branching

Reexamination Certificate

active

06823448

ABSTRACT:

BACKGROUND
This invention relates to exception handling in a processor.
A programmable microprocessor, such as a digital signal processor, typically includes exception handling hardware for dealing with errors that may be encountered while processing instructions. For example, the processor may encounter illegal instructions (unsupported opcodes), misaligned instructions, instructions that access protected areas of memory, illegal memory addresses, bus errors and the like.
In the event such an error is detected, the exception handler hardware typically invokes a corresponding software routine, often referred to as an error handler, for responding to the error condition.


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Dale, et al., “Pipeline Processor Exception Control Mechanism”,IBM Technical Disclosure Bulletin, vol. 24, No. 11A, Apr. 1982, p. 5530.
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Garcia, et al., “Storage Access-Exception Detection for Pipelined Execution Units”,IBM Technical Disclosure Bulletin, vol. 25, No. 12, May, 1983, pp. 6711-6712.

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