Exception handling in a processor that performs speculative out-

Details Exception handling in a processor that performs speculative out- Exception handling in a processor that performs speculative out-

1997-05-05

1999-11-16

Myers, Paul R.

Electrical computers and digital processing systems: processing

Processing control

Branching

712239, G06F 900

Patent

active

059876000

ABSTRACT:
A method and circuitry for coordinating exceptions in a processor. The processor generates a result data value and an exception data value for each instruction wherein the exception data value specifies whether the corresponding instruction causes an exception. The processor commits the result data values to an architectural state of the processor in the sequential program order, and fetches an exception handler to processes the exception if the exception is indicated by one of the exception data values. The processor fetches an asynchronous event handler to processes an asynchronous event if the asynchronous event is detected while the result data values are committed to the architectural state of the processor.

REFERENCES:
patent: 4912707 (1990-03-01), Kogge et al.
patent: 4970641 (1990-11-01), Hester et al.
patent: 4985825 (1991-01-01), Webb, Jr. et al.
patent: 5193156 (1993-03-01), Yoshida et al.
patent: 5193158 (1991-10-01), Kinney et al.
patent: 5226126 (1993-07-01), McFarland et al.
patent: 5297263 (1994-03-01), Ohtsuka et al.
patent: 5355457 (1994-10-01), Shebanow et al.
patent: 5367705 (1994-11-01), Sites et al.
patent: 5694564 (1997-12-01), Alsup et al.
patent: 5740393 (1998-04-01), Vidwans et al.
Instruction Issue Logic for High-Performance, Interruptable, Multiple Functional Unit, Pipelined Computers Sohi IEEE Trans on Comp vol. 39 No. 3 Mar. 1990 pp. 349-359.
Hwu & Patt, "Checkpoint Repair for High Performance Out-of-Order Execution Machines" Dec. 1987 IEEE Transactions on Computers vol. C36 pp. 1496-1514.
Hwu & Patt "Checkpoint Repair for Out-of-Order Execution Machines" 1987 pp. 18-26.
"A Multiple Out-of-Order Instruction Issuing System for Superscalar Processors" Harry Dwyer III Aug. 1991 Chapter 7.
"Checkpoint Repair for High-Performance Out-of-Order Execution Machines", IEEE Transactions on Computers, (C6), Wen-Mei W. Hwu and Yale N. Patt, Dec. 1987, pp. 1496-1514.
Sohi, et al.; Instruction Issue Logic for High-Performance, Interruptable Pipelined Processors; Computer Sciences Dept., University of Wisconsin-Madison, ACM 1987; pp. 27-34.
Weiss, et al.; Instruction Issue Logic in Pipelined Supercomputers; IEEE Transactions on Computers, vol. c-33, No. 11, Nov. 1984; pp. 1013-1022.
Robert M. Keller; Look-Ahead Processors; Computing Surveys, vol.7, No. 4, Dec. 1975; pp. 177-195.
Riseman, et al.; The Inhibition of Potential Parallelism by Conditonal Jumps; IEEE Transactions of Computers, Dec. 1972; pp. 1405-1411.
Tjaden, et al.; Detection and Parallel Execution of Independent Instructions; IEEE Transactions on Computers, vol. C-19, No. 10, Oct. 1970; pp. 889-895.
Foster, et al.; Percolation of Code to Enhance Parallel Dispatching and Execution; IEEE Transactions on Computers, Dec. 1972; pp. 1411-1415.
James E. Smith; Implementation of Precise Interrupts in Pipelined Processors; IEEE, 1985; pp. 36-44.
Hwu, et al.; HPSm2: A Redefined Single-ship Microengine: System Sciences; The Computer Society of the IEEE 1988; pp. 30-39.
Hwu, et al.; Exploiting Horizontal and Vertical Concurrency via the HPSm Microprocessor; ACM 089791-250-0/87/0012/0154 1987; pp. 154-161.
Hwu, et al.; Design Choices for the PHSm Microprocessor Chip; Computer Science Sivision, University of California, Berkeley; Proc. of the 20th Annual Hawaii International Conf. on System Sciences, Kona, Jan. 1987; (seven pages).
Hwu, et al.; HPSm, a High Performance Retricted Data Flow Architecture Having Minimal Functionality; IEEpp. 297-306.
Gharachorloo, et al.; Detecting Violations of Sequential Consistency; to appear in SPAA '91; pp. 1-11.
Gharachorloo, et al.; Two Techniques to Enhance the Performance of Memory Consistency Models; To appear in ICPP '91; pp.
R.M. Tomasulo; An Efficient Algorithm for Exploiting Multiple Arithmetic Units; IBM Technical Journal, vol. 11, Jan. 1967 pp. 25-33.
V. Popescu, et al., "The Metaflow Architecture", IEEE Micro, 1991, pp. 10-13, and 63-73.
Mike Johnson, "Superscalar Microprocessor Design", Prentice Hall, 1991.

Affiliated with

Also associated with

Rating

Exception handling in a processor that performs speculative out- does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Exception handling in a processor that performs speculative out-, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Exception handling in a processor that performs speculative out- will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1338620