Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Counting – scheduling – or event timing
Reexamination Certificate
1999-06-22
2003-07-01
Butler, Dennis M. (Department: 2185)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
Counting, scheduling, or event timing
Reexamination Certificate
active
06587958
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to the generation of timing signals in a digital system and more particularly to the generation of timing signals in a computer system.
COPYRIGHT NOTICE/PERMISSION
A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure as it appears in the Patent and Trademark Office patent file or records, but otherwise reserves all copyright rights whatsoever. The following notice applies to the software and data as described below and in the drawings hereto: Copyright© 1999, Microsoft Corporation, All Rights Reserved.
BACKGROUND OF THE INVENTION
The evolution of the hardware architecture of personal computers has not kept pace with the real time tasks that modern operating systems are asked to perform. For example, modern operating systems are asked to synchronize audio and video data streams. To perform this task successfully, an operating system needs access to timing signals that resolve time into fractions of microseconds. Unfortunately, today's hardware architectures are typically only capable of resolving time into microseconds.
The fixed frequencies used in personal computer timers are so low that the timers are not useful for performing many of the timing operations required in personal computers. One strategy for avoiding this limitation involves the use of “timing loops,” in which a loop containing a group of instructions is calibrated and subsequently time is measured in terms of the number of iterations of the timing loop. For example, while booting an operating system a “timing loop” may be calibrated by first executing the loop twenty million times. The time to execute each pass through the loop is computed by dividing the execution time, obtained by reading a timer, by twenty million. Having calibrated the timing loop, a programmer may now measure time increments smaller than the finest timer increment by executing a “timing loop.”
Unfortunately, this approach has several problems: First, there are external factors that can affect how fast the processor executes a timing loop. For example, a device performing I/O reads on the processor buss slows the execution of a timing loop. Second, while the processor is executing a timing loop, it isn't doing any other useful work. Third, modem computers have dynamically variable clock speeds. If for example, the machine gets too hot, the speed of the processor may be lowered so that it cools down. This requires timing loops to be re-calibrated each time the processor changes speed, which is impractical.
Another problem with the hardware architecture of many personal computer platforms is that the event timer interface is byte oriented. A byte oriented interface requires the use of many instructions to program the event timer, which makes the process of programming the timer a slow process. The time to program a timer may be reduced by executing code on a faster processor, but unfortunately, this is a very expensive solution.
For these and other reasons there is a need for the present invention.
SUMMARY OF THE INVENTION
The above-mentioned shortcomings, disadvantages and problems are addressed by the present invention, which will be understood by reading and studying the following specification.
Real time processing and timing of events in a computerized system is enabled by the use of a timer including memory mapped registers aligned on sixty-four bit word boundaries and a high frequency clock. Such a timer is easily programmed using a single assembler instruction to communicate with each of the memory mapped registers and is capable of providing both periodic and one-shot interrupts to a processing unit in the computerized system. Periodic interrupts enable an operating system to perform pre-emptive scheduling. Each interrupt provides the operating system with an opportunity to review the queued workload and reassign the processor to a different task, if necessary. One-shot interrupts enable the real time processing of single events.
A computerized system capable of supporting real time processing includes several components. A processing unit provides a platform on which an operating system and application programs can execute. A timer, capable of being controlled by the operating system, provides periodic and one-shot interrupts to the operating system for the timing of events. The timer includes a high frequency clock that drives two or more memory mapped counters which send interrupts to the operating system. The timer also includes a memory mapped reload register. The memory mapped reload register defines whether a memory mapped counter rolls over after decrementing to zero, or whether the memory mapped counter reloads to a value other than the rollover value after decrementing to zero. A memory mapped interrupt register coupled to the processing unit and at least one of the memory mapped counter registers stores an interrupt generated by the counters.
REFERENCES:
patent: 5363499 (1994-11-01), Glass
patent: 5463761 (1995-10-01), Culley
patent: 5964882 (1999-10-01), Dey
Motorola Time Processor Unit Reference Manual, 1993, pp. 1-1 through 2-20.*
“CHMOS Programmable Interval Timer”,Intel specification 82C54, 1-18, (Oct., 1994).
Oshins Jacob K.
Richards David
Butler Dennis M.
Leydig Voit & Mayer Ltd
Microsoft Corporation
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