Event driven dynamic logic for reducing power consumption

Details Event driven dynamic logic for reducing power consumption Event driven dynamic logic for reducing power consumption

2005-12-20

2005-12-20

Le, Don (Department: 2819)

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Field-effect transistor

C326S092000, C326S028000

Reexamination Certificate

active

06977528

ABSTRACT:
Methods and circuits are described for reducing power consumption within digital logic circuits by blocking the passage of clock signal transitions to the logic circuits when the clock signal would not produce a desired change of state within the logic circuit, such as at inputs, intermediary nodes, outputs, or combinations. By way of example, the incoming clock is blocked if a given set of logic inputs will not result in an output change of state if a clock signal transition were to be received. By way of further example, the incoming clock is blocked in a data flip-flop if the input signal matches the output signal, such that receipt of a clock transition would not produce a desired change of state in the latched output. The invention may be utilized for creating lower power combinatorial and/or sequential logic circuit stages subject to less unproductive charging and discharging of gate capacitances.

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Krambeck, R.H. et al.; “High-Speed Compat Circuits With CMOS,” IEEE Journal of Solid-State Circuits, vol. SC-17, No. 3, pp. 614 thru 619, Jun. 1982.
Kang, Sung-Mo (Steve) et al.; “Dynamic Logic Circuits,” Chapter 9 from CMOS Digital Integrated Circuits, Analysis and Design, Third Edition, McGraw Hill, New York, New York, Cover page, Bibliographic page, pp. 357 thru 404, (2003).

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