Event driven digital signal processor with time constraints

Details Event driven digital signal processor with time constraints Event driven digital signal processor with time constraints

2003-09-22

2010-10-19

Chan, Eddie P (Department: 2183)

Electrical computers and digital processing systems: processing

Processing control

Logic operation instruction processing

C713S323000, C713S401000, C713S501000

Reexamination Certificate

active

07818549

ABSTRACT:
The present invention relates to an event driven digital signal processor1comprising: a central arithmetical unit5, a register4, a controller3, an instruction memory2, and input/output devices. The instruction memory2is arranged to include time performance constraints and events. An event control unit6is arranged to recognize an event and to control processing to be carried out as a consequence of the event while fulfilling the time performance constraints. The controller3is arranged to suspend processing of the time performance constraints after initiating operations in the event control unit6. The controller3resumes processing when advised by the event control unit6.

REFERENCES:
patent: 4497023 (1985-01-01), Moorer
patent: 5220676 (1993-06-01), LoGalbo et al.
patent: 5517628 (1996-05-01), Morrison et al.
patent: 5768602 (1998-06-01), Dhuey
patent: 5826072 (1998-10-01), Knapp et al.
patent: 5913058 (1999-06-01), Bonola
patent: 6292887 (2001-09-01), Janniello
patent: 6308197 (2001-10-01), Mason et al.
patent: 6567839 (2003-05-01), Borkenhagen et al.
patent: 6892167 (2005-05-01), Polan et al.
patent: 2004/0088704 (2004-05-01), Owen et al.
Patterson, David. Hennessy, John. “Computer Archetecture: A Quantitative Approach”. Morgan Kaufmann Publishers, Inc. 1996. pp. 278-282.
Ixthos, Inc.,Overview of Real-Time Multiprocessing, 1996.
Gerndt R. et al. “An event-driven multi-threading architecture for embedded systems”; Hardware/Sofware CoDesign, 1997. Proceedings of the Fifth International Workshop on Braunschweig, Germany Mar. 24-26, 1997 pp. 29-33.
Zoran Salcic, et al. “Reflex: A Processor Core for Reactive Embedded Applications”; Mainstream 12th International Conference; vol. 2438/2002, Sep. 2, 2002; pp. 945-954.
Baganne et al., “Hardware interface design for real time embedded systems” 1997. Proceedings. Seventh Great Lakes Symposium on Urbana-Champaign, IL Mar. 13-15, 1997.

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