Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output command process
Reexamination Certificate
1999-05-19
2001-08-21
Lee, Thomas (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output command process
C710S020000, C703S016000, C703S017000
Reexamination Certificate
active
06279046
ABSTRACT:
RELATED APPLICATIONS
This patent application is related to the following patent applications: U.S. patent application, entitled “Apparatus and Method for Specifying Maximum Interactive Performance in a Logical Partition of a Computer System Independently from the Maximum Interactive Performance in Other Partitions,” Ser. No. 09/314,541 filed May 19, 1999 by Armstrong et al.; U.S. patent application, entitled “Processor Reset Generated via Memory Access Interrupt,” Ser. No. 09/314,769 filed May 19, 1999 by Armstrong et al.; U.S. Patent Application R
0999-023
, entitled “Management of a Concurrent Use License in a Logically-Partitioned Computer,” Ser. No. 09/314,324 filed May 19, 1999 by Armstrong et al.; and U.S. Patent Application, entitled “Logical Partition Manager and Method,” Ser. No. 09/314,214 filed May 19, 1999 by Armstrong et al.
FIELD OF THE INVENTION
The invention is generally related to computers and computer software. In particular, the invention is generally related to management of multiple logical partitions in a logically-partitioned computer.
BACKGROUND OF THE INVENTION
Computer technology continues to advance at a rapid pace, with significant developments being made in both software and in the underlying hardware upon which such software executes. One significant advance in computer technology is the development of multi-processor computers, where multiple computer processors are interfaced with one another to permit multiple operations to be performed concurrently, thus improving the overall performance of such computers. Also, a number of multi-processor computer designs rely on logical partitioning to allocate computer resources to further enhance the performance of multiple concurrent tasks.
With logical partitioning, a single physical computer is permitted to operate essentially like multiple and independent “virtual” computers (referred to as logical partitions), with the various resources in the physical computer (e.g., processors, memory, input/output devices) allocated among the various logical partitions. Each logical partition executes a separate operating system, and from the perspective of users and of the software applications executing on the logical partition, operates as a fully independent computer.
A shared resource, often referred to as a “hypervisor” or partition manager, manages the logical partitions and facilitates the allocation of resources to different logical partitions. As a component of this function, a partition manager maintains separate virtual memory address spaces for the various logical partitions so that the memory utilized by each logical partition is fully independent of the other logical partitions. One or more address translation tables are typically used by a partition manager to map addresses from each virtual address space to different addresses in the physical, or real, address space of the computer. Then, whenever a logical partition attempts to access a particular virtual address, the partition manager translates the virtual address to a real address so that the shared memory can be accessed directly by the logical partition.
An important design rule that is enforced in most logically-partitioned computers is that the virtual address space of each logical partition is completely inaccessible to other logical partitions. Strict policies are enforced by the partition manager to limit access to the virtual addresses within a logical partition's address space to only that logical partition. Furthermore, logical partitions are not permitted to access memory using real addresses so that a logical partition is not able to corrupt the memory of another partition by using a real address that it does not own. By doing so, each logical partition is better able to emulate a separate physical computer, and applications that are originally designed for a non-partitioned computer are often able to execute within a logical partition without modification or customization.
An undesirable side effect of the strict memory access rules, however, is that communication between logical partitions is typically very restricted. Since each logical partition operates as if it were a separate physical computer, typically the only form of inter-partition communication is via a conventional network interface, in much the same manner as any computer would utilize to communicate with another physical computer on a network. To implement such an interface, often each logical partition is assigned a separate network adaptor resource in the computer, and the actual communication passes from one network adaptor on the physical computer, over an external network to which both network adaptors are connected, and back to the other network adaptor on the computer. Communications in this manner can be relatively slow and cumbersome, and typically relatively expensive, at least as compared to internal communications within the processing core of a computer.
Therefore, a significant need exists in the art for an improved manner of permitting communication between the logical partitions within a computer, while still conforming to the memory access controls that maintain the independence of each logical partition.
SUMMARY OF THE INVENTION
The invention addresses these and other problems associated with the prior art by providing an apparatus, program product, and method that utilize an event-driven communications interface to support communications between multiple logical partitions in a logically-partitioned computer, particularly where each logical partition operates in an independent address space from other logical partitions. The event-driven communications interface is at least partially disposed within a partition manager that is accessible to each of the logical partitions.
In embodiments consistent with the invention, events are typically passed between logical partitions in the form of messages that are passed first from a source logical partition that initiates the event, through the partition manager, and then to a target logical partition to which the event is directed. Passage of events between logical partitions typically occurs completely through the internal hardware components of the computer, and usually with relatively little overhead, thereby providing performance that is superior to the use of external networks and the like. Also, by passing such messages between logical partitions in the form of events, communications can occur without compromising the independence of the address spaces of the logical partitions.
These and other advantages and features, which characterize the invention, are set forth in the claims annexed hereto and forming a further part hereof. However, for a better understanding of the invention, and of the advantages and objectives attained through its use, reference should be made to the Drawings, and to the accompanying descriptive matter, in which there is described exemplary embodiments of the invention.
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Armstrong William Joseph
Nayar Naresh
Cao Chun
International Business Machines - Corporation
Lee Thomas
Wood Herron & Evans L.L.P.
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