Event based semiconductor test system

Details Event based semiconductor test system Event based semiconductor test system

1999-06-28

2004-01-13

Broda, Samuel (Department: 2123)

Data processing: structural design, modeling, simulation, and em

Simulating electronic device or electrical system

Circuit simulation

C703S017000, C703S027000, C714S738000, C714S742000

Reexamination Certificate

active

06678643

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to a semiconductor design and test system for designing and testing semiconductor integrated circuits such as a large scale integrated (LSI) circuit, and more particularly, to an event based semiconductor IC design and test system for testing a semiconductor IC by generating an event based test pattern produced directly from logic simulation data produced in a design stage of the semiconductor IC through a CAD (computer aided design) process.
BACKGROUND OF THE INVENTION
FIG. 1
is a schematic block diagram showing an example of a semiconductor test system for testing a semiconductor integrated circuit (hereafter may also be referred to as “IC device”, “LSI under test” or “device under test”).
In the example of
FIG. 1
, a test processor
11
is a dedicated processor provided within the semiconductor test system for controlling the operation of the test system through a tester bus. Based on pattern data from the test processor, a pattern generator
12
provides timing data and waveform data to a timing generator
13
and a wave formatter
14
, respectively. A test pattern is produced by the wave formatter
14
with use of the waveform data from the pattern generator
12
and the timing data from the timing generator
13
, and is supplied to a device under test (DUT)
19
through a driver
15
.
A response signal from the DUT
19
resulted from the test pattern is converted to a logic signal by an analog comparator
16
with reference to a predetermined threshold voltage level. The logic signal is compared with expected value from the pattern generator
12
by a logic comparator
17
. The result of the logic comparison is stored in a fail memory
18
corresponding to the address of the DUT
19
. The driver
15
, the analog comparator
16
and switches (not shown) for changing pins of the device under test are provided in a pin electronics
20
.
In a process of developing semiconductor integrated circuits such as a large scale integrated (LSI) circuit, almost always, a design method using a computer aided design (CAD) tool is employed. Such a design environment using a CAD tool is also referred to as an electronic design automation (EDA) environment.
In such a semiconductor development process in an EDA environment, desired semiconductor circuits are created in an LSI with the use of a hardware description language such as VHDL and Verilog. Also in this process, functions of the semiconductor circuits thus designed are evaluated on a computer with use of a software simulator called a device logic simulator.
A device logic simulator includes an interface commonly called a testbench through which test data (vector) is applied to the device design data (device model) showing the intended semiconductor circuits, and the resultant responses of the intended semiconductor circuits are evaluated.
After the design stage of the LSI circuit, actual LSI devices are produced and are tested by a semiconductor test system such as an LSI tester to determine whether the LSI devices perform the intended functions properly. As noted above, an. LSI tester supplies a test pattern (test vector) to an LSI device under test and compares the resultant outputs of the LSI device with expected data to determine pass/fail of the LSI device.
For testing an LSI device which has a higher level of functionality and density, a test pattern to be applied to the LSI device must accordingly be complex and lengthy, resulting in significantly large workloads and work hours in producing the test pattern.
Thus, to improve an overall test efficiency and productivity of the semiconductor integrated circuits, an attempt has been made to use the data produced through the execution of the device logic simulator in an actual test of the semiconductor integrated circuits. This is because the test procedure performed by the LSI tester in testing an actual semiconductor integrated circuit has a substantial similarity with a test procedure by the device logic simulator in testing the design data of the semiconductor circuit in the CAD process noted above.
For example, an attempt is made to produce test patterns and expected value patterns for an LSI tester to test the intended semiconductor integrated circuits by utilizing the data (dump file) resultant from executing the device logic simulation.
FIG. 2
is a schematic diagram showing an overall relationship between a design stage of a semiconductor integrated circuit and a test stage of the semiconductor integrated circuit. This example shows a situation where a very large scale integrated circuit (LSI), such as a system-on-chip (SoC)
23
is designed under an electronic design automation (EDA) environment.
After designing the semiconductor integrated circuit
23
under the EDA environment, it is obtained a design data file and a test data file
33
. Through various data conversion processes, the design data is converted to physical level data indicating each gate in the designed semiconductor integrated circuit. Based on the physical level data, an actual integrated circuit
29
is produced in a semiconductor integrated circuit production process (silicon process).
The integrated circuit thus produced is tested by a semiconductor test system
30
. By executing a logic simulation by a testbench
34
with use of the test data derived through the design stage of the integrated circuit, a data file
35
showing input-output relationships in the integrated circuit is created. An example of such a data file is VCD (Value Change Dump) of Verilog.
As will be described in more detail later, a format conversion process is performed by a conversion software
37
so that the VCD data file
35
described in an event base format is converted to a test signal of a cycle base format. As a consequence, a test pattern in the cycle base is stored in a file
38
in the semiconductor test system
30
. A hardware tester
39
applies the test pattern to the device under test
29
for testing the device functions and the like.
As briefly mentioned above, in such logic simulation data, test patterns to be applied to a device model as well as the resultant outputs (expected value patterns) of the device model are expressed by an event base format. Here, the event base data expresses the points of change (events) in a test pattern from logic “1” to logic “0” or vice versa with reference to the passage of time. Generally, such time passages are expressed by time lengths from a predetermined reference point (absolute time difference) or a time length from a previous event (relative time difference).
In contrast, in an actual LSI tester (semiconductor test system), test patterns are described by a cycle base format. In the cycle base format data, each variable in a test pattern is defined relative to each test cycle (tester rate) of the LSI tester. Thus, as will be explained in more detail later, in a typical LSI tester, a test pattern for a corresponding test cycle is formed based on descriptions of a test cycle (tester rate), waveform (kind of waveform and edge timings), and vector in test pattern data.
As in the foregoing, the existing LSI testers deal with the data in the cycle base while the data produced through the EDA environment is in the event base. Thus, to effectively create test patterns for testing semiconductor devices actually produced based on the CAD data obtained in the design stage of the semiconductor device, it is necessary to convert the event base data to the cycle base data.
Accordingly, in.
FIG. 2
noted above, the conversion software
37
extracts the pattern data and timing data from the dump file
35
which is derived from executing the device logic simulation in the design stage of the semiconductor device. The conversion software
37
converts the extracted data to the cycle base data. The pattern data and timing data thus converted to the cycle base format include descriptions regarding the test cycles (tester rate), waveforms (types of waveforms, edge timings), and vectors. The pattern data and timing data are stored in the pat

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