Evasion of power on self test during an operating system...

Details Evasion of power on self test during an operating system... Evasion of power on self test during an operating system...

2011-07-19

2011-07-19

Connolly, Mark (Department: 2115)

Electrical computers and digital processing systems: support

Digital data processing system initialization or configuration

C713S002000

Reexamination Certificate

active

07984282

ABSTRACT:
A system and method to evade the power on self test during an operating system initiated reboot is disclosed. In one embodiment, a method for optimizing reboot process of a computer includes determining a status of a power on self test (POST) performed during a prior booting of the computer when an operating system (OS) initiated rebooting of the computer is triggered, loading information obtained during the POST of the prior booting of the computer into a basic input output system (BIOS) of the computer if the status of the POST performed during the prior booting of the computer indicates a success of the POST, and performing the rebooting of the computer using the information, wherein a subsequent POST associated with the rebooting of the computer is skipped during the rebooting of the computer.

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patent: 2006/0294352 (2006-12-01), Morrison et al.

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