Evaluation phase expansion for dynamic logic circuits

Details Evaluation phase expansion for dynamic logic circuits Evaluation phase expansion for dynamic logic circuits

1996-05-31

1999-03-23

Santamauro, Jon

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

326 97, H03K 19096, H03K 1900

Patent

active

058865403

ABSTRACT:
An evaluation phase expansion system for increasing the operating frequency of a dynamic logic circuit which includes a plurality of logic stages. The plurality of logic stages are partitioned into a first set of logic stages which are responsive to an early clock signal and which evaluate in an early evaluate phase and a second set of logic stages which are responsive to a late clock signal and which evaluate in a late evaluate phase. The late evaluate phase of the late clock signal commences during the early evaluate phase of the early clock signal and terminates during an early pre-charge phase of the early clock signal in order to artificially induce clock asymmetry to compensate for logic asymmetry in alternating pipeline phases of the dynamic logic circuit.

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U.S. application No. 08/609306, Naffziger, filed Mar. 1, 1996.

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