Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
2008-09-18
2010-10-05
Hollington, Jermele M (Department: 2829)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
C324S537000, C257S758000
Reexamination Certificate
active
07807998
ABSTRACT:
An evaluation pattern for evaluation of lateral hillock formation is provided with a lattice pattern; and an isolated metallization. The lattice pattern includes: a loop interconnection; and lattice interconnections laterally and vertically arranged to intersect with one another so that a region surrounded by the loop interconnection is divided into a plurality of sub-regions arranged in rows and columns. The width of the lattice interconnections is narrower than the width of the loop interconnection. The isolated metallization is provided in an outmost one of the sub-regions, the outmost one being surrounded by the loop interconnection and corresponding ones of the lattice interconnections.
REFERENCES:
patent: 6710449 (2004-03-01), Hyoto et al.
patent: 6943129 (2005-09-01), Hyoto et al.
patent: 2003/0049945 (2003-03-01), Hyoto et al.
patent: 2004/0101996 (2004-05-01), Hyoto et al.
patent: 2004/0155316 (2004-08-01), Saito et al.
patent: 2008/0023815 (2008-01-01), Asai et al.
patent: 2008/0038851 (2008-02-01), Koyama et al.
patent: 5-315335 (1993-11-01), None
Hollington Jermele M
McGinn IP Law Group PLLC
NEC Electronics Corporation
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