Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
2001-03-29
2002-08-27
Ho, Hoai V. (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
C438S011000, C438S014000, C438S015000, C438S018000
Reexamination Certificate
active
06441397
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor evaluation apparatus for evaluating chargeup damage of an actual device in the semiconductor device fabrication process.
BACKGROUND OF THE INVENTION
Following the requirement of fineness in the semiconductor device fabrication process, ion implantation technique, plasma dry etching technique, and the like have been introduced in semiconductor device fabrication apparatuses and a semiconductor substrate is to be exposed frequently to an electron, ions, plasma, and the like and thus how to suppress a chargeup damage has come up as a matter in the fabrication process.
Further, requirements for fineness of elements and variety of devices are further acceleratedly increased following the system large scale integration (LSI) and the effect of the chargeup damage has become a more sensible matter for an element. Nevertheless, its mechanism and the measurement method have not yet sufficiently established and most part of the matter has been left unclear today.
Conventional evaluation methods of the chargeup damage are mainly a breakdown voltage measurement method for an ultra thin oxide film and a method using an antenna MOS transistor, an EPROM, an EEPROM and the like.
The former is a method for checking whether a gate oxide film is broken or not by using an ultra thin oxide film or checking breakdown property (TDDB: Time dependent Dielective Breakdown) with the lapse of time by forcibly applying stress by charging with electric charge.
This method is to measure the deterioration of the oxide film caused when the charged up and accumulated electric charge penetrates the gate oxide film with an ultra thin film thickness through and reaches a substrate. Problems are that the ultra thin oxide film used is not used in the relevant fabrication process and that dielectric breakdown is natural to take place if the evaluation is carried out using a thinner film to make judgment difficult.
A substrate already bearing an oxide film and produced in the outside is mounted in some cases and inserted directly in an apparatus in other cases and thus the evaluation sometimes considerably deviates from the fabrication process and the device structure. Further, since the measurement is carried out in a distraction mode, the method is insufficient in the sensitivity to detect the property alteration which does not result in the distraction mode of an actual device.
Actually, evaluation is impossible in many cases in the fabrication process of an actual device of such as a bipolar IC and an analog element of CCD. Also, the method has disadvantages that a large pattern surface area is required, it takes a long time to evaluate, and that a large number of samples are required for getting statistic data.
In the method using an antenna MOS transistor, there are many cases of using an ultra thin oxide film for the gate oxide film and in such cases, the same problems as described above are brought forth. Since evaluation is carried out in a MOS transistor, evaluation of the transistor properties and the hot carrier life properties is also made possible other than the evaluation of the withstand voltage property of the gate oxide film and the TDDB property.
Further, since the gate is composed as to have an antenna structure, actual pattern addition is possible and also evaluation of actual dry etching and resist removal in the fabrication process is made possible.
However, an electrode for measurement has to be installed in an antenna gate for evaluation measurement and for that, the charge accumulated in a floating gate is possibly discharged at the time of the process of forming a layer for the electrode.
Hence, the method probably misses the phenomenon that the gate is broken and deteriorated by the electric charge since the electric charge together with remaining charge is expelled to the antenna in the process, for example, in the film formation process by plasma oxide, after the process of layer formation for electrode.
In case of employing this method for evaluating the transistor properties by their alteration, the sensitivity is improved more than that by the withstand voltage evaluation, however in the case where the ultra thin oxide is used, it becomes difficult to make validity of the results in relation to an actual product and the actual fabrication process. Further, it also becomes difficult to grasp to which extent of the chargeup the property's alteration value is related to and to judge the chargeup is positive or negative.
In the case of employing the EEPROM, EPROM or other memory device, in many cases, the chargeup phenomenon is evaluated based on the alteration of the memory properties by setting a produced product or device as it is in an apparatus. The problems in such cases are whether the product or device can be set as it is in the apparatus and that the treatment in the actual process cannot be carried out and the device structure is different from that in the actual fabrication process.
Hence, if the evaluation is possible, it is unclear what the evaluation results imply in the actual product and the actual fabrication process of the product. Nevertheless, the extent of the chargeup can be measured based on the output electric current value and Vth, which are properties of a memory, the method gives clearer evaluation results than the former methods as above described.
Also, although the imperfect judgment, the method makes it possible to grasp whether the chargeup is positive or negative within the operation range.
Regarding the problems in the present techniques, that the evaluation element cannot be produced in the relevant process is a main and big obstacle and due to that, evaluation is carried out by way of using the ultra thin oxide film and an element such as EEPROM, EPROM with the different structure.
If the process and the device structure are different, the resistance of the contact face with a capacity and an apparatus differs and thus it can easily be supposed that the chargeup state is also different from that in the actual process and the actual product. Even in the dry etching process, actually a material to be etched is etched and an underlayer material is over etched in the situation that a resist is patterned. It is desirable that the chargeup can be evaluated at that time.
Further, although the chargeup phenomenon is supposedly affected with the CVD process, metal film growth, thermal treatment, and the like before and after the etching process and also with the hydrogen content in the film, the well structure, the wiring structure, and the like, it has not sufficiently been made clear.
DISCLOSURE OF THE INVENTION
The state of the art is described above, mainproblems arethat the measurement sensitivity is low, the measurement evaluation takes a long time, evaluation is impossible for analog elements, the evaluation constitution is insufficient to evaluate the chargeup damage caused in the actual fabrication process, the evaluation is impossible to evaluate the chargeup damage relevant to the actual product on completion of the diffusion process, and that no correlation of the evaluation results with the properties of the actual product and actual devices is made clear.
Objects of the present invention is:
1. to improve the measurement sensitivity relevant to the chargeup damage;
2. to shorten the measurement evaluation time relevant to the chargeup damage;
3. to find the chargeup damage occurring process;
4. to make evaluation possible for digital and analog elements (MOS, a bipolar IC, the CCD process);
5. to equalize evaluation to that in the actual product by simulation of the actual process and the entire process; and
6. to make a relation of the chargeup damage with the properties of the actual product and the actual device.
The means for solving the above described objects 1 to 6 are as follows:
1. to employ a floating type antenna gate or diffusion layer and both N channel and P channel elements;
2. to employ a manner of employing the numerical evaluation by using an element for
Ho Hoai V.
Huynh Andy
Matsushita Electronics Corporation
Parkhurst & Wendel LLP
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