Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
1999-12-14
2001-08-28
Nguyen, Viet Q. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185180, C365S185140, C365S185010, C365S185020
Reexamination Certificate
active
06282122
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to the field of integrated circuit memory technology. More specifically, the present invention provides techniques of evaluating characteristics of nonvolatile programmable memory cells and enhancing the reliability and service life of these memory cells.
Memory cells are used in the implementation of many types of electronic devices and integrated circuits. These devices include microprocessors, static random access memories (SRAMs), erasable-programmable read only memories (EPROMs), electrically erasable programmable read only memories (EEPROMs), Flash EEPROM memories, programmable logic devices (PLDs), field programmable gate arrays (FPGAs), application specific integrated circuits ASICs), among others. Memory cells are used to store the data and other information for these and other integrated circuits.
As integrated circuit technology and semiconductor processing continue to advance, there is a need for greater densities and functionality in integrated circuits, which are often determined in a large part b the size of the memory cells. Further, it is desirable that the memory cells have improved operating characteristics, such as lower power consumption, nonvolatility, greater device longevity, improved data retention, better transient performance, superior voltage and current attributes, and improvements in other similar attributes.
There is a further need for improved techniques of evaluating the physical characteristics of nonvolatile memory cells. These physical characteristics or properties are important in the determination of an integrated circuit's service life and reliability. These measurements are also useful for study and use in improving memory cells. One property of a memory cell is margin, including program and erase margin, indicating the degree to which a cell is in a programmed or erased state. The degree of margin comes from a determination of the threshold voltages in the programmed and erased states. In particular, the voltage threshold (VTE) of erased nonvolatile memory cells such as EEPROM or Flash cells may be negative. Present techniques only allow threshold measurements in the positive range. Using these techniques, a device with a negative erased threshold voltage is presumed to have an erased threshold voltage of zero volts. However, the value of the erased threshold voltage is important in characterizing the reliability and service life of a memory cell, and it is important to be able to measure negative threshold voltage.
As can be seen, improved techniques for evaluating margin of memory devices are needed, especially when the memory devices have negative erased threshold voltages. Improved techniques are also needed for improving the reliability and longevity of these memory devices.
SUMMARY OF THE INVENTION
The present invention provides techniques for characterizing memory devices, and in particular nonvolatile memory devices such as EEPROM and Flash cells. Specifically, the techniques of the present invention allow the measurement of negative threshold voltages. Erased nonvolatile memory cells will have negative threshold voltages in some implementations. The techniques of the present invention may be used to measure these negative values. Furthermore, the techniques of the present invention are also applicable to the measurement of similar characteristics or properties in many other situations. The present invention also provides for techniques to improve the reliability and longevity of memory cells.
Specifically, the present invention is a method of evaluating a threshold voltage of a programmed device including the following: sweeping a voltage range including negative voltages at a control gate line of the program device; and determining a voltage at which the program device begins to conduct. An embodiment of the present invention includes negatively biasing a substrate connection of the programmed device. An embodiment of the present invention includes elevating a source node of the program device with an offset voltage.
A further embodiment of the present invention includes decoupling memory cells adjacent to a selected memory cell by placing a negative voltage on control gates of the adjacent memory cells. An embodiment of the present invention includes decoupling memory cells adjacent to a selected memory cell by negatively biasing substrate connections of the adjacent memory cells. An embodiment of the present invention includes decoupling memory cells adjacent to a selected memory cell by placing a voltage on terminals of the adjacent memory cells such that a gate-to-source voltage for each cell is less than a turn-on threshold of the cell.
An embodiment of the present invention further provides techniques of operating a memory cell including coupling an offset voltage to source nodes of a plurality of memory cells; and determining a stored state of a selected one of the memory cells while the offset voltage is coupled to the source nodes.
Other objects, features, and advantages of the present invention will become apparent upon consideration of the following detailed description and the accompanying drawings, in which like reference designations represent like features throughout the figures.
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Altera Corporation
Nguyen Viet Q.
Townsend and Townsend / and Crew LLP
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