Evaluation method for wirings of semiconductor device

Details Evaluation method for wirings of semiconductor device Evaluation method for wirings of semiconductor device

1998-06-25

2000-07-18

Mintel, William

Active solid-state devices (e.g., transistors, solid-state diode

Test or calibration structure

257758, 324519, 324765, 438393, H01L 2358

Patent

active

060910801

ABSTRACT:
Electromigration (EM) of a multilayer wiring is evaluated accurately and efficiently. A capacitance measuring wiring is disposed through the third insulator film in parallel to the second testing wiring. A stress current is sent to the second testing wiring toward the first testing wiring for a period and subsequently the capacitance of the capacitor composed of the second testing wiring and the capacitance measuring wiring is measured. The volume of voids in the second testing wiring is obtained from the ratio of this capacitance and the capacitance before letting the stress current flow. EM is evaluated by defining the wiring life span by using this volume.

REFERENCES:
patent: 4620145 (1986-10-01), Dietz et al.
patent: 5684304 (1997-11-01), Smears
patent: 5686759 (1997-11-01), Hyde et al.
patent: 5757027 (1998-05-01), Kuchta
patent: 5777486 (1998-07-01), Hsu

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