Evaluation circuit for reading out an information item...

Details Evaluation circuit for reading out an information item... Evaluation circuit for reading out an information item...

2002-03-18

2004-03-23

Phan, Trong (Department: 2818)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S203000, C365S185200, C365S185210

Reexamination Certificate

active

06711080

ABSTRACT:

The invention relates to an evaluation circuit for reading out the information stored in a memory cell in accordance with the preamble of Patent claim
1
.
U.S. Pat. No. 5,889,702 describes an evaluation circuit for an EPROM, in which two auxiliary current sources are respectively connected in parallel with the cell to be measured and with a reference cell. The current sources in this case serve for setting the operating point of a current mirror.
Integrated memory modules having memory cells in which binary information items are stored, such as e.g. EPROMs, DRAMs or SRAMs, are widespread. In order to assess the information stored in the memory cell, the current (read-out current) carried on the bit line is assessed.
With increasing integration of the cell structures far into the sub-micron range—the intention is to achieve structural dimensions down to 0.13 micrometer—the cell current becomes smaller and smaller and, accordingly, the read-out speed of the cells also decreases. On the other hand, the clock frequencies of the memory modules and thus the access speed become higher and higher, with the result that the small cell currents constitute a serious problem.
In the case of very high miniaturization of the cells, it is hardly possible to distinguish the cell current of a conducting cell from the cell current of a non-conducting cell, which makes the assessment particularly difficult. In the case of very high miniaturization, the cell current window, i.e. the difference between conducting cell and non-conducting cell, becomes ever smaller. In order that the read access time, that is to say the time required for determining the stored information, is kept as short as possible, one possibility is to reduce the bit line capacitance. However, this requires larger memory modules.
However, this requires smaller sectors. This means, however, that the number of sectors and the associated area overhead increases for a given storage capacity. The area overhead increases significantly with increasing miniaturization. On the other hand, the required memory demand in the applications increases. The overall result of this is an unacceptable disadvantage in respect of area.
Another possibility for increasing the cell current would be, e.g. to apply higher gate voltages to the transistor of the memory cells. However, on the one hand, this would necessitate additional voltage sources, and charge pumps arranged on the chip would require an excessively large area in order to take account of this alternative. On the other hand, increasing the gate voltage is generally unacceptable for reasons of reduced reliability. The problems which arise with the application of conventional measuring devices are illustrated by way of example in
FIGS. 1-3
.
FIG. 1
shows a known evaluation circuit for reading out the cell current of a memory cell
1
, said cell current being carried on a bit line
3
, with an evaluation path
7
and a reference path
8
.
The evaluation path
7
comprises the memory cell
1
with a floating gate transistor
11
, a bit line decoder
2
with selection transistors
12
, and a precharge and converter circuit
4
for precharging the bit line capacitance
5
and for converting the read-out current I
Meas
. The memory cell
1
, the bit line decoder
2
and the precharge and converter circuit
4
are connected in series in this case.
The bit line capacitances
5
and
18
are in each case parasitic capacitances.
The evaluation circuit illustrated in
FIG. 1
operates according to the differential principle and has a reference path
8
constructed symmetrically with respect to the evaluation path
7
. The evaluation circuit furthermore comprises a current or voltage comparator
13
, which is in each case connected to the precharge and converter circuit
4
and
14
, respectively, and compares the (amplified) read-out current of the evaluation path
7
with the (amplified) reference current of the reference path
8
or corresponding voltages with one another. Common-mode interference, in particular, is suppressed by means of the differential principle.
As already mentioned, the reference path
8
comprises a circuit arrangement constructed symmetrically with respect to the evaluation path
7
, with a precharge and converter circuit
14
, a dummy decoder
15
and a memory cell
16
with a floating gate transistor
17
.
FIG. 2
shows the typical profile of the read-out current I
meas
for a non-conducting and a conducting cell.
The read-out of the cell current by the evaluation circuit
10
comprises a precharge phase, in which the parasitic bit line capacitance
5
is charged, and an evaluation phase, in which the read-out current I
Meas
is compared with the reference current I
ref
and a corresponding output value is output.
The precharge and evaluation phases can be effected either simultaneously or temporally successively. The former method has the advantage of faster assessment, while the latter method has a lower energy consumption.
FIG. 2
shows the profile of the read-out current I
Meas
in the case of an assessment according to the serial principle for a non-conducting cell (left-hand half of the figure) and a conducting cell (right-hand half of the figure).
The cell transistor
11
is deactivated (V
G
=0) during the precharge phase, a current flowing (V
G
≠0) through the transistor
11
only during the evaluation phase, i.e. for times t>t
1
or t
2
.
FIG. 2
a
shows the characteristic current profile for a non-conducting cell. The form of the charging current and thus also the duration of the precharge phase are determined by the parasitic bit line capacitance
5
.
The changeover instant between the precharge phase and the evaluation phase is determined by a reference current which is variably adjustable and is usually set approximately in the middle of the maximum current flowing through the memory cell, i.e. from I
Cell
1 to I
Cell
2.
FIG. 2
a
shows two reference currents I
ref1
and I
ref2
for memory cells with a different structural dimension, the index “2” denoting the cell with the higher integration. As can be seen in
FIG. 2
b
, the cell currents I
Cell
decrease with higher integration.
The read-out current I
Meas
falls below the respective reference current at the instant t
1
and t
2
(cf.
FIG. 2
c
); this specifies the duration of the precharge phase and the beginning of the evaluation phase.
In the case of a conducting cell (cf.
FIG. 2
b
), the evaluation operation begins when the charging current reaches the reference current I
ref
. In this case, the assessment yields a logic “1”, since the cell current I
Cell
lies above the reference current.
In the case of the non-conducting cell of
FIG. 2
a
, the read-out current I
Meas
lies below the respective reference current I
ref
starting from the instant t
1
and t
2
, so that a logic “0” is output by the evaluation circuit.
FIG. 3
shows an assessment of a memory cell according to the dynamic principle, in the case of which a cell current flows from the beginning of the measurement (the gate voltage of the transistor
11
is V
G
≠0).
In the case of the non-conducting cell, the read-out current I
Meas
falls below the corresponding reference current I
ref
after a time t
1
and t
2
. For the smaller cell (I
ref2
), the measurement instant is shifted by &Dgr;t
0
relative to the less highly integrated cell (I
ref1
) (cf.
FIG. 3
c
).
Proceeding from the worst case, in which the bit line capacitance is completely charged, in the case of a conducting cell the read-out current I
Meas
exceeds the corresponding reference current I
ref1
and I
ref2
at the instant t
3
and t
4
, respectively, as is shown in
FIGS. 3
b
and
3
d
. Relative to the less highly integrated cell, the measurement instant is shifted by &Dgr;t
1
, relative to the less highly integrated cell (I
ref1
) (cf.
FIG. 3
d
).
The object of the present invention, therefore, is to provide an evaluation circuit with which significantly faster read-out times are achieved.
This object is achieved according to the invention by means of

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