Ethernet memory management system and methods for operation...

Details Ethernet memory management system and methods for operation... Ethernet memory management system and methods for operation...

1999-11-18

2004-02-24

Kizou, Hassan (Department: 2662)

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

C370S412000, C370S429000, C711S171000

Reexamination Certificate

active

06697366

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to an ethernet controller memory management apparatus and its control method. More specifically, the present invention relates to an ethernet controller's memory control equipment that stores received data from the ethernet controller in memory and its control method.
BACKGROUND OF THE INVENTION
Communication networks such as computer networks are increasingly used in interconnecting a plurality of computers each of which independently executes tasks while communicating information over the network for shared use. The volume of information which may be transferred over such networks has increasingly become more demanding on the structure of the networks themselves. Various network devices are known to allow the connection of a greater number of computers to a single network and further to allow more free communication of information between computers or other devices on the network or on other interconnected networks. The protocols related to communication of information on a network typically further provide for checking whether or not various computers on the network are transmitting and/or receiving data within a single network or between different networks. Various hubs or repeaters are known which manage data exchanges within and between networks. As the number of devices on networks increases, the demands for high performance repeaters and other devices to meet the challenge of managing the information flow so that the data does not create a bottleneck effect on the network are increasingly required. Furthermore, the protocol supporting communications over such networks are typically evolving to support higher data rates and larger volumes of information transmittal over the communication networks.
One example of such a communication protocol is known as the ethernet protocol.
FIG. 1
is a schematic diagram of a representative ethernet frame according to Institute of Electrical and Electronic Engineers (IEEE) 802.3 standard. Such ethernet networks typically use a Carrier Sense Multiple Access/Collision Detection (CSMA/CD) protocol as a collision detection and recovery mechanism. A CSMA/CD type computer (terminal) generally checks carriers on a transmission path of the network before transmitting frames. The computer then transmits a frame during what appears to the terminal to be an idle period on the transmission path. However, such networks allow collisions to occur when two different connected computers both attempt to transmit frames on the network at the same time. When the collision is detected, the ethernet protocol provides for collision recovery steps including stopping transmission of any remaining parts of a frame currently being transmitted and initiating retransmission of transmission frames which encounter the collision after some time interval which is typically specified by the collision detection recovery protocol in use on the network. Accordingly , as the CSMA/CD communication method involves the use of shared transmission media (or channels) the collision detection functions and the retransmission functions supporting frame transmission are preferably implemented in the physical layer and the data link layer of a multi-layer communications protocol as are known to those of skill in the art.
As shown in
FIG. 1
, an IEEE 802.3 ethernet frame generally includes a preamble, a starting frame delimiter (SFD), a destination address, a source address, a length or ethertype, information data, and a frame check sequence (FCS). The preamble is used to adjust bit synchronization to match the transmission and receiving speed of a transmitting device to the transmission and receiving speed of a receiving device. The SFD is a bit array used for frame synchronization which indicates the start of an available frame. The destination address indicates an address of a destination ethernet card controller to which the frame is to be transmitted. The source address indicates an address of the transmitting ethernet controller device. The length or ethertype indicates the length of information data contained in a frame or, alternately, determines ethernet types. The information data is the available data which is being communicated and may also contain padding, i.e., a portion filled with zeros (or ones) when the amount (length) of available data is less than a minimum length of a frame. The FCS is used to detect errors in a received frame, typically through the use of a check sum applied to the bits of the frame excluding the preamble and the SFD.
FIGS. 2
a
and
2
b
are schematic diagrams illustrating an ethernet controller respectively transmitting and receiving frames. Referring first to
FIG. 2
a
, when transmitting data, a direct memory access (DMA)
2
in the ethernet controller reads data to be transmitted from a memory
1
and transmits the data to a media access control (MAC)
3
which is typically a sub-layer of the data link layer. The MAC
3
in turn transmits the data to the physical layer, adding the preamble, SFD, padding, and FCS. The central processing unit (CPU) (not shown) then typically provides predefined addresses of the transmitting device and the receiving device, which are stored in memory, to the DMA
2
during data transmission.
Referring to
FIG. 2
b
, when receiving data, the MAC
3
′ transmits the data received from the physical layer to the DMA
2
′, typically excluding the preamble and SFD. The DMA
2
′ stores the received data in the memory
1
′ without requiring help from the CPU (not shown).
The CPU reports an address of the data to be transmitted and a storage address of the received data respectfully to the DMA
2
,
2
′ through a frame descriptor at the time of transmitting and/or receiving data. More particularly, the frame descriptor is typically assigned to an associated memory location by the CPU, and read through the use of a frame descriptor pointer.
FIG. 3
is a schematic diagram illustrating a frame descriptor which may be used with existing ethernet controllers. The illustrated single frame descriptor
5
is mapped into a frame at the time of transmitting and/or receiving data. As shown in
FIG. 3
, the frame descriptor
5
includes a data pointer
5
a
, a status field
5
b
, a length field
5
c
, a control field
5
d
and a descriptor pointer
5
e
. The data pointer
5
a
may be a 32-bit pointer to indicate a first or starting address of a memory location where data received or to be transmitted is stored in memory. The status field
5
b
has bits to indicate a status of transmission and receiving and which may further indicate error types. The length field
5
c
indicates a length (amount) of data contained in the frame to be transmitted and/or received. The control field
5
d
is used to assign methods to transmit and receive frames. The descriptor pointer
5
e
has an address of a next frame descriptor which is next to (sequentially linked to) the current frame descriptor
5
. In other words, a plurality of frame descriptors may be provided with a linked list sequential structure.
FIG. 4
is a schematic diagram representing operations related to the transmission and/or receipt of data over an ethernet protocol network using a frame descriptor as described with reference to
FIG. 3
in the ethernet controller. As shown in
FIG. 4
, the frame descriptor pointer
10
, independently from the frame descriptors
20
through
22
, manages a plurality of frame descriptors
20
,
21
,
22
which are associated in a linked list structure. That is, the frame descriptor pointer
10
contains the address of the currently operative frame descriptor
20
, and, when the current frame descriptor
20
is utilized to store or retrieve data for communication, the address contained in the frame descriptor pointer
10
is updated with a value of a descriptor pointer
20
e
, that is, a value indicating the address of a frame descriptor
21
coupled sequentially next to the current frame descriptor
20
. As noted above, a plurality of frame descriptors
20

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