Etching process utilizing the same positive photoresist layer fo

Details Etching process utilizing the same positive photoresist layer fo Etching process utilizing the same positive photoresist layer fo

1976-06-30

1977-08-09

Powell, William A.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

156247, 156344, 156656, 156657, 156659, 156661, 204192S, 427 88, 427 89, H01L 21306, C23F 102

Patent

active

040408914

ABSTRACT:
In integrated circuit fabrication a method is provided involving the utilization of the same positive photoresist layer to form two different masks used in two separate etching steps. A positive photoresist layer is formed on a substrate, and portions of the positive photoresist layer are selectively exposed and developed to form the photoresist mask having a pattern of openings therethrough exposing the underlying substrate. Then, the substrate exposed in these openings is etched to form the pattern of recesses in the substrate corresponding to the openings. Next, portions of the remaining photoresist layer respectively adjacent to openings in the photoresist layer are exposed and developed to laterally expand such openings, after which the substrate exposed in these expanded openings is etched whereby the portions of the recesses underlying the original openings are etched deeper than the portions of the recesses underlying the expanded portions of said openings. The result is a two-level recess pattern.
In accordance with an important aspect of the disclosure, the substrate being etched is a layer of electrically insulative material formed over an integrated semiconductor circuit member, and the deeper portions of the recesses are etched completely through the insulative layer to form holes which may be used for the passage of contacts to a semiconductor substrate where the insulative layer is directly on the substrate or as via holes when the insulative layer is formed between two layers of integrated circuit metallurgy.

REFERENCES:
patent: 3542551 (1970-11-01), Rice
patent: 3649393 (1972-03-01), Hatzakis
patent: 3853576 (1974-12-01), Netznik
patent: 3858304 (1975-01-01), Leedy et al.
patent: 3878008 (1975-04-01), Gleason et al.

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