Etching process of CoSi2 layers

Details Etching process of CoSi2 layers Etching process of CoSi2 layers

2000-01-06

2001-07-03

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Chemical etching

Liquid phase etching

C438S048000, C216S100000, C216S108000, C216S109000

Reexamination Certificate

active

06255227

ABSTRACT:

BACKGROUND OF THE INVENTION
The use of cobalt disilicide (CoSi
2
) in microelectronics applications is becoming more and more important. In CMOS technology, with the scaling down of dimensions, especially for CMOS technology manufacturing of a transistor with a gate length smaller than 0.35 &mgr;m, CoSi
2
has become an attractive material due to its better characteristics when compared to the more frequently used titanium disilicide (TiSi
2
).
The interaction of a silicide film with chemicals and reactive gasses during further processing is an important issue in maintain the integrity of the film in the fully integrated structure. TiSi
2
is known to be very reactive with chemicals such as ammonium hydroxide (NH
4
OH—) and hydrogen fluoride-based (HF-based) solutions. CoSi
2
is much more robust in that respect. In general, wet etching of CoSi
2
is considered very difficult.
SUMMARY OF THE INVENTION
The present invention relates to an etching process for CoSi
2
layers in semiconductor processing. Specifically, the present invention relates to methods for accurately controlling the etching rate of CoSi
2
layers in semiconductor processing by adjusting the pH of an HF-based solution. The pH of this solution is regulated by adding pH modifying chemicals to the HF-based solution. Preferably, the pH modifying chemicals are H
2
SO
4
or HCl (in order to reduce the pH) or NH
4
OH (in order to increase the pH of the HF-based solution). The HF-based solution can be a buffered solution or not.
In one aspect of the present invention, the pH of the HF-based solution is from about 0 to about 1.5 in order to have a rather fast etching rate of the CoSi
2
layer.
In another aspect of the present invention, the pH of the HF-based solution is from about 1.5 to about 5.5 in order to have a lower, but basically constant etching rate.
In yet another aspect of the present invention, the pH of the HF-based solution is from about 5.5 to about 14 in order to have no or at least insignificant etching rate of CoSi
2
. This aspect of the invention is preferred for obtaining a selective etch of an oxide spacer while no etching of CoSi
2
layer occurs in the integration process for active transistors using self-aligned pocket implantation.
The present invention also relates to the use of this etching process for the formation of Schottky barrier infrared detectors. One aspect of the present invention is the manufacturing of Schottky barrier infrared detectors which are improved over those currently available. This aspect of the invention is particularly useful for Schottky barrier infrared detectors with CoSi
2
/Si interface. Preferably, the Schottky barrier infrared detector has a CoSi
2
/Si
1-x
Ge
x
interface.
In addition, the present invention relates to the use of the etching process as a process step for self-aligned pocket implantation in semiconductor devices. Furthermore, the present invention relates to the use of the etching process to obtain selective etching.
A further aspect of the present invention is to improve the process of self-aligned pocket implantation using oxide spacers in semiconductor manufacturing process. More particularly, this aspect relates to the use of a specific process step based on selective etching of CoSi
2
, while the other conventional process steps are still maintained. Thus, use of the present invention has little effect on the global costs of whole process integration in active transistors fabrication.
The present invention also relates to a method of manufacturing CoSi
2
/Si Schottky barrier infrared detectors comprising the steps of:
a) growing a Si
1-x
Ge
x
layer on a silicon substrate;
b) growing a Si sacrificial layer on the top of the Si
1-x
Ge
x
layer;
c) depositing a Co layer on said Si sacrificial layer;
d) heating the Co layer in order to obtain a CoSi
2
layer;
e) depositing a photoresist strip on said CoSi
2
layer;
f) developing the photo-resist strip using a masking layer in order to create the required patterning of the CoSi
2
layer;
g) etching the CoSi
2
layer with a HF-based solution having a pH value smaller than 1.5; and
h) removing the photoresist strip.
Preferably, the Schottky barrier infrared detectors are CoSi
2
/Si
1−x
Ge
x
Schottky barrier infrared detectors.
Another aspect of the present invention is a method of self-aligned pocket implantation in an active transistor having a small gate length comprising the steps of:
a) defining an active area within a semiconductor substrate with a source region, a drain region and a gate region;
b) defining a silicon oxide spacer in between said source and said gate and in between said drain and said gate;
c) forming a CoSi
2
top layer selectively on said drain, gate, and source regions;
d) etching the silicon oxide spacer using a HF-based solution having a pH higher than 3; and
e) implanting dopants in order to achieve a pocket implantation self-aligned towards said gate region and said CoSi
2
, top layer.
In one aspect of the above embodiment, the HF-based solution is a buffered solution having a pH of about 4.5. In another aspect of the above embodiment, the dopants are of the opposite kind for the source and drain implants. In yet another aspect of this embodiment, the dopants are of the same kind for the source and drain implants. In a further aspect of the above method, the transistor is a CMOS transistor having a gate length less than 0.35 &mgr;m.


REFERENCES:
patent: 5605865 (1997-02-01), Maniar et al.
patent: 5821175 (1998-10-01), Engelsberg
patent: 5937319 (1999-08-01), Xiang et al.
patent: 6048405 (2000-04-01), Skrovan et al.
patent: 6074960 (2000-06-01), Lee et al.
patent: 6120354 (2000-09-01), Koos et al.

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