Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2003-02-03
2004-07-27
Lee, Hsien-Ming (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S637000, C438S638000, C438S671000, C438S672000, C438S700000, C438S712000, C438S717000
Reexamination Certificate
active
06767825
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a process for manufacturing of the damascene structure of the semiconductor device, and more particularly to an etching process for forming the damascene structure of the semiconductor device.
2. Description of the Prior Art
When semiconductor devices of integrated circuits (IC) become highly integrated, the surface of the chips can not be supplied with enough area to make the interconnects. For matching the requirement of interconnects increases with Complementary Metal-Oxide-Semiconductor (CMOS) devices shrinks, many designs of the integrated circuit have to use dual damascene method. Moreover, it is using the three-dimensional structure of multi-level interconnects at present in the deep sub-micron region, and inter-metal dielectric (IMD) as the dielectric material which is used to separate from each of the interconnects. A conducting wire which connects between the upper and the lower metal layers is called the via plug in semiconductor industry. In general, if an opening, which forms in the dielectric layer exposure to devices of the substrate in, interconnects, it is called the contact hole.
It has two methods for conventional via and interconnect processes, one method is the via and interconnect finish by oneself, wherein the method is that the dielectric is first formed on the metal layer, and then the photoresist layer (PR) is defined on the dielectric, and use the etching process to make the via, and deposit conduction material in the via by means of deposition to finish the via process, then deposit and define metal layer, final, deposit the dielectric layer whereon. Conventional forming metal interconnect process is that make the via and the interconnect by means of two lithography process. Thus, it needs cumbrous steps of deposit and pattern. And yet, it will result in difficult patterned interconnects due to the multi layer connect layout is more daedal in the sub-quarter micron. Therefore, damascene interconnect structure is developed at present. According to particulars of the process, it will compartmentalize three types, such as the single type, the dual type and the self-aligned type. The damascene is that etch the trench of interconnects in the dielectric, and then fill the metal as interconnect. This method can introduce metal that is difficult etched into the semiconductor without etching in the interconnect process. Therefore, this invention is the best method of the interconnect process in the sub-quarter micron.
Conventional dual damascene include two patterns, one is the deep patterns, that is the via patterns or via-first scheme; another is the shallow patterns or the line patterns, that is the trench patterns or trench-first scheme. For production manufacturing of deep sub-micro devices, the photoresist and nonmetal/metal hard-mask layers with much less etch-resistant wavelength are often implemented in the dual-damascene etching process. In the conventional dual-damascene structure, it easily induced the large defects of carbon residues in the Cu CMP process if the CMP slurry directly polishes onto the low-k dielectric film, and the SiC layer is one of the candidate dielectric films to cap on the low-k materials and to serve as CMP polish stop layer for preventing the generation of CMP defects. For example, in the trench-first process scheme, the partial via etching was carried out after hard-mask open, and the dual-damascene structure was simultaneously formed during the trench etching. However, because of slight oxidation in the surface of SiC layer, especially in the dual hard-mask film stack of oxide/SiC, it is difficult to etch SiC layer. In accordance with the above description, a new and improved method for forming the damascene structure is therefore necessary, so as to raise the yield and quality of the follow-up process.
SUMMARY OF THE INVENTION
In accordance with the present invention, a new method for forming the damascene structure is provided that substantially overcomes drawbacks of above mentioned problems raised from the conventional methods.
Accordingly, one of the objects in the present invention provides an etching process for forming the damascene structure. The present invention utilizes two-steps etching process to etch the hard-mask layer so as to form the damascene structure. Furthermore, in this invention, the two-steps etching process comprises a breakthrough step and an etching step, wherein the breakthrough step utilizes a CF
x
-based mixed-gas, such as Ar/O
2
/CF
4
, to slightly flush out the top surface of the hard-mask layer for removing the remained polymer and oxidized residues; and further, the etching step utilizes a mixed-gas having chlorine, such as Cl
2
/O
2
, to pre-etch the hard-mask layer and partial dielectric layer until forming an opening in the dielectric layer, and then the damascene structure is formed by this structure. Therefore, this invention can effectively arise the performance, the quality and yield of the semiconductor process such that this invention corresponds to economic effect and utilization in industry, and it is appropriate for deep sub-micron technology.
In accordance with the present invention, a new etching process for forming the damascene structure is provided. First of all, a semiconductor substrate with a first dielectric layer thereon is provided, and then both the first and second hard-mask layers are sequentially formed on the first dielectric layer, wherein the first hard-mask layer is served as the polished-stop layer in the follow-up chemical mechanical polishing process (CMP). Then a first photoresist layer is formed and defined on the second hard-mask layer as the etching mask to perform a first etching process, so as to etch through the second and the first hard-mask layers until a predetermined thickness in the first hard-mask layer, whereby a first opening having a first pattern is formed on the first hard-mask layer. After removing the first photoresist layer, a breakthrough process is performed for removing the polymer and oxidized residues remained on top surface of the second and the first hard-mask layers, wherein the breakthrough process utilizes a CF
x
-based mixed-gas, such as Ar/O
2
/CF
4
, to slightly flush out the top surface of the second and the first hard-mask layers so as to strip the polymer and oxidized residues remained thereon. Afterward, a second dielectric layer is formed on the second hard-mask layer and the first opening is filled with that, wherein the material of the second dielectric layer can serve as the anti-reflection coating layer (ARC) or the bottom anti-reflection coating layer (BARC). Next, a second photoresist layer is formed and defined on the second dielectric layer, and then a second etching process is performed by the second photoresist layer as an etching mask to etch through the second dielectric layer and the first hard-mask layer until a first predetermined thickness of the first dielectric layer, and form a second opening having a second pattern in the first dielectric layer. After removing the second photoresist layer and the second dielectric layer, a third etching process is performed by the second hard-mask layer as an etching mask to etch through the first hard-mask layer and the first dielectric layer until exposing the semiconductor substrate, wherein the first hard-mask layer can retard the etching rate of the first opening during the third etching process, and the third etching process utilizes the mixed gas having chlorine, such as O
2
/Cl
2
, so as to adjust the etching selectivity by the mixing ratio of the chlorine in the mixed gas, that is, the mixing ratio of the chlorine in the mixed gas is higher, the etching selectivity of the first to the second hard-mask layer is higher. Finally, the second hard-mask layer is removed to form a dual-damascene structure in the dielectric layer.
REFERENCES:
patent: 6394104 (2002-05-01), Chen et al.
patent: 6457477 (2002-10-01), Young et al.
patent: 6468916 (2002-10-01), Choi e
Arent Fox
Lee Hsien-Ming
United Microelectronics Corporation
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