Etching of structures with high topography

Details Etching of structures with high topography Etching of structures with high topography

2008-07-01

2008-07-01

Estrada, Michelle (Department: 2823)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S694000, C438S697000, C257SE21245, C257SE21305

Reexamination Certificate

active

07393768

ABSTRACT:
The present invention relates to a method for the patterning of a stack of layers on a surface with high topography. A method of the present invention can be used for gate patterning for multiple Gate FETs (MuGFETs), for patterning of the control gate in non-volatile memory applications, and for the patterning of the poly emitter in BiCMOS devices. The present invention also relates to a device prepared by a method of the invention.

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European Search Report for related Eurpoean Application No. EP 05447052.1, mailed on Feb. 8, 2006.

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