Etching high aspect contact holes in solid state devices

Details Etching high aspect contact holes in solid state devices Etching high aspect contact holes in solid state devices

1996-03-19

1999-12-28

Niebling, John

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438723, 438724, 438743, 438744, 438952, H01L 2128

Patent

active

06008121&

ABSTRACT:
Contact holes through a dielectric are formed by forming a layer of polysilicon having a thickness between 0.02 um and 0.15 um inclusive on the dielectric, forming a layer of resist having a thickness between 0.4 um and 0.6 um inclusive on the layer of polysilicon, making a mask of the layer of resist, using it to form a mask in the layer of polysilicon and etching contact holes in the dielectric by exposing it to etching gasses through the apertures in the polysilicon mask. When the dielectric includes a layer of oxide adjacent the polysilicon mask and a layer of nitride between it and elements of the device, the resist mask is removed prior to etching the contact hole and a gas mixture of: C.sub.4 F.sub.8 ; one of Ar, H, F; CO; CF.sub.4 or C.sub.2 F.sub.6 is used. Contact holes are made through a dielectric to conductors in a substrate by the same method, and desired cross sections are obtained by using a second resist mask and a selective etch for the polysilicon followed by a selective etch for the dielectric. These structures can be stacked and suitable interconnections made by the described method. Contact holes to gate electrodes can be etched using the basic process.

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