Etch stops and alignment marks for bonded wafers

Details Etch stops and alignment marks for bonded wafers Etch stops and alignment marks for bonded wafers

1999-08-30

2002-04-16

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Total dielectric isolation

C438S691000, C438S692000, C156S922000

Reexamination Certificate

active

06372600

ABSTRACT:

TECHNICAL FIELD
This invention relates generally to bonded wafers, and more particularly to a method of manufacturing a bonded wafer, the bonded wafer made by the method, and integrated circuits manufactured from chips on such wafers.
BACKGROUND OF THE INVENTION
Bonded wafers are fabricated with a single crystal substrate wafer bonded to a single crystal silicon device wafer. The substrate wafer provides structural strength to the bonded wafer and is relatively thicker, while the device wafer in which devices are subsequently formed is relatively thinner. A surface of each of the substrate wafer and the device wafer are polished to be planar. The polished surfaces are placed in contact with each other and the wafers are subjected to a high temperature heat treatment which bonds the wafers together. There may or may not be an oxide layer formed on the substrate wafer, the device wafer, or both of the wafers, prior to bonding. With an oxide layer on at least one of the wafers prior to bonding, the oxide layer forms an oxide layer between the substrate wafer and the device wafer when the substrate wafer and device wafer are bonded.
Bonded wafers in which buried layers are required for device fabrication are made by bonding a device wafer to a substrate wafer as described above. Subsequent to being bonded, the device wafer is thinned by removing material from a major exposed surface until the device wafer is thinned to a predetermined thickness, such as 1 to 2&mgr;. Buried or diffused layers, of N-type or P-type, or both, are implanted into the device wafer portion of the bonded wafer. An epitaxial layer of N or P type material is grown to the desired thickness over the device wafer portion of the bonded wafer.
Any known technique, including but not limited to plasma etching, ion etching, grinding or polishing, may be used to ablate a surface of the device wafer. When removing material from the major exposed surface of the device wafer portion of the bonded wafer to thin the device wafer to the predetermined thickness, it is difficult to control the thickness of the device wafer portion of the bonded wafer that remains after the thinning process. Furthermore, it is difficult to align subsequent device diffusions with the buried layers in the device wafer portion of the bonded wafer.
What is needed is a technique to precisely control the thickness of the device wafer portion of the bonded wafer when the device wafer is thinned. It is also desirable to have an accurate alignment feature to align subsequent device diffusions with buried layers in the device wafer.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method of making a bonded wafer by diffusing regions of a first wafer, first major surface. Trenches are etched a predetermined distance into the first wafer from the first major surface toward a second major surface. The first major surface and trenches are coated with oxide. The first major surface of the first wafer is bonded to a second wafer to form a bonded wafer. The second major surface of the bonded wafer which is also the second major surface of the first wafer is ablated until oxide in the trenches is detected. The bonded wafer is cut into chips which are packaged as integrated circuits.


REFERENCES:
patent: 5091330 (1992-02-01), Cambou et al.
patent: 5258318 (1993-11-01), Buti et al.
patent: 5308776 (1994-05-01), Gotou
patent: 5413941 (1995-05-01), Koos et al.
patent: 5439551 (1995-08-01), Meikle et al.
patent: 5459104 (1995-10-01), Sakai
patent: 5484738 (1996-01-01), Chu et al.
patent: 5504033 (1996-04-01), Bajor et al.
patent: 5536675 (1996-07-01), Bohr
patent: 5683932 (1997-11-01), Bashir et al.
patent: 5728621 (1998-03-01), Zheng et al.
patent: 5872043 (1999-02-01), Chen
patent: 2001/0000497 (2001-04-01), Epshteyn et al.
patent: 000623423 (1994-09-01), None
patent: 10-264017 (1998-10-01), None
patent: 11 58225 (1999-03-01), None
patent: 11 77517 (1999-03-01), None
Patent No. 4312732, filed on Mar. 10, 1980 and issued on Jan. 26, 1982 to Degenkolb et al.

Affiliated with

Also associated with

Rating

Etch stops and alignment marks for bonded wafers does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Etch stops and alignment marks for bonded wafers, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Etch stops and alignment marks for bonded wafers will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2882836