Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
1999-08-04
2001-06-05
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S706000, C438S710000, C438S721000, C438S197000, C438S585000, C438S592000
Reexamination Certificate
active
06242362
ABSTRACT:
BACKGROUND OF THE INVENTION
1) Field of the Invention
This invention relates generally to fabrication of semiconductor devices and more particularly to an etch process for fabricating a vertical hard mask/conductive pattern profile.
2) Description of the Prior Art
In semiconductor fabrication, metal structures are commonly formed by patterning one or more blanket conductive layers. These blanket conductive layers typically have a blanket hard mask layer formed thereover. The hard mask layer protects the underlying conductive layer from damage during etching of higher layers as well as preventing diffusion into and out of the underlying conductive layer. One material that is often used to form a hard mask layer over a polysilicon conductive layer is silicon oxynitride. However, patterning a polysilicon layer and silicon oxynitride hard mask layer using prior art processes can result in a T-shaped hard mask conductive layer profile, reducing the width of the conductive structure thus formed. It is desireable to provide a method of patterning a hard mask and underlying conductive layer which can maintain a more vertical profile.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering the following Patents.
U.S. Pat. No. 5,139,968 (Hayase et al.) teaches a method for forming a T-shaped gate electrode.
U.S. Pat. No. 5,407,870 (Okada et al.) discloses a process for forming a SiON layer.
U.S. Pat. No. 5,766,993 (Tseng) discloses a process for forming a poly gate and contact.
U.S. Pat. No. 5,700,739 (Chiang et al.) discloses an oxynitride hard mask and etch process using a reactive ion etch with a fluorine containing ethant.
U.S. Pat. No. 5,731,239 (Wong et al.) shows a silicon oxynitride hard mask and a salicide process.
U.S. Pat. No. 5,766,974 (Sardella) shows an oxynitride layer on an intervener dielectric to provide an etch stop for a Cl
2
overetch.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method for fabricating a vertical hard mask/conductive pattern profile.
It is another object of the present invention to provide a method for fabricating a vertical silicon oxynitride hard mask/conductive patern profile using a low temperature to deposit the hard mask layer.
To accomplish the above objectives, the present invention provides a method of fabricating a vertical hard mask/conductive pattern profile using a low temperature SiON deposition to form the hard mask layer, and a special Cl
2
/He—O
2
/N
2
etch chemistry to etch the SiON hard mask, the conductor (WSix & poly), and the gate oxide.
The process begins by forming a polysilicon or more preferably a polycide conductive layer over a semiconductor substrate. A silicon oxynitride hard mask layer is deposited at low temperature over the conductive layer. The silicon oxynitride hard mask layer is patterned to form a hard mask pattern. The conductive layer is patterned to form a conductive pattern. The silicon oxynitride hard mask releases oxygen during the conductive layer etch. The inventors have found that the oxygen can prevent polymer formation on the sidewalls of the conductive pattern resulting in an undesirable T-shaped hard mask/conductive pattern profile (e.g. the width of the hard mask is greater than the width of the conductive pattern after etching). In the present invention, an etch using Cl
2
/He—O
2
/N
2
chemistry prevents undercutting, resulting in a desirable vertical hard mask
1
conductive layer profile.
The present invention provides considerable improvement over the prior art. The key advantage of the present invention is that it prevents the etching process from forming an undercut in the conductive layers underlying the silicon oxynitride hard mask. The inventors believe that nitrogen containing etch chemistry of the present invention prevents undercutting by forming a C-N polymer which deposits on the sidewalls of the conductive layer (polysilicon and/or tungsten silicide) protecting the conductive layers from overetching.
Another important advantage of the invention is the deposition temperature for the silicon oxynitride hard mask. Silicon oxynitride can be deposited at about 400° C., using a chemical vapor deposition process. Conventional furnace silicon nitride deposition requires a temperature of about 800° C. The invention's lower temperature for SiON is important in high speed DRAM devices because the conventional high temperature for silicon nitride deposition can adversely effect sheet resistance for the titanium silicide source/drain contacts used in such devices.
REFERENCES:
patent: 5139968 (1992-08-01), Hayase et al.
patent: 5407870 (1995-04-01), Okada et al.
patent: 5700739 (1997-12-01), Chiang et al.
patent: 5731239 (1998-03-01), Wong et al.
patent: 5766974 (1998-06-01), Sardella et al.
patent: 5766993 (1998-06-01), Tseng
patent: 5876796 (1999-03-01), Regolini et al.
patent: 5930627 (1999-07-01), Zhou et al.
patent: 5948703 (1999-09-01), Shen et al.
patent: 6008139 (1999-12-01), Pan et al.
patent: 6022776 (2000-02-01), Lien et al.
patent: 6046103 (2000-04-01), Thei et al.
patent: 6069086 (2000-05-01), Nallon et al.
patent: 6077738 (2000-06-01), Lee et al.
patent: 6096613 (2000-08-01), Wu
patent: 2 285 336 (1995-07-01), None
Hsaio Yung-Kuan
Lin Huan-Just
Liu Jen-Cheng
Tsai Chia-Shiung
Ackerma Stephen B.
Bowers Charles
Saile George O.
Smoot Stephen W.
Stoffe William J.
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