Etch-back process for failure analysis of integrated circuits

Adhesive bonding and miscellaneous chemical manufacture – Delaminating processes adapted for specified product – Delaminating in preparation for post processing recycling step

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156664, 156662, 20419232, 437923, 437948, H01L 21308

Patent

active

049800191

ABSTRACT:
An apparatus and a method to inhibit sputtering of undesirable material on to a dielectric layer of an integrated circuit being etched. After exposing the integrated circuit within its package, the leads of the integrated circuit are electrically coupled together by a metallic foil. The metallic foil is wrapped about the package to also provide thermal coupling, however, the integrated circuit is left exposed. Then, the integrated circuit is placed onto an etch-resilient plate disposed atop a cathode electrode. An opening in the plate allows direct placement of the integrated circuit onto the cathode. An etch-resilient cover is placed above the plate opening and the integrated circuit, but the cover has an opening to expose the integrated circuit. During etching, the cover inhibits sputtering from the leads, preform and bond wires.

REFERENCES:
patent: 4376692 (1983-03-01), Tsukada et al.
J. C. Wood, IBM Technical Disclosure Bulletin, vol. 24, No. 7A, Dec. 1981, Cleaning of Metal Surfaces by Ion-Etching.

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